2 from litex
.build
.generic_platform
import *
3 from litex
.build
.xilinx
import XilinxPlatform
, VivadoProgrammer
5 # IOs ----------------------------------------------------------------------------------------------
9 ("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")),
12 ("user_led", 0, Pins("M21"), IOStandard("LVCMOS33")),
13 ("user_led", 1, Pins("N20"), IOStandard("LVCMOS33")),
14 ("user_led", 2, Pins("L21"), IOStandard("LVCMOS33")),
15 ("user_led", 3, Pins("AA21"), IOStandard("LVCMOS33")),
16 ("user_led", 4, Pins("R19"), IOStandard("LVCMOS33")),
17 ("user_led", 5, Pins("M16"), IOStandard("LVCMOS33")),
21 Subsignal("cs_n", Pins("T19")),
22 Subsignal("mosi", Pins("P22")),
23 Subsignal("miso", Pins("R22")),
24 Subsignal("vpp", Pins("P21")),
25 Subsignal("hold", Pins("R21")),
26 IOStandard("LVCMOS33")
31 Subsignal("tx", Pins("E14")),
32 Subsignal("rx", Pins("E13")),
33 IOStandard("LVCMOS33"),
39 "U6 V4 W5 V5 AA1 Y2 AB1 AB3",
42 IOStandard("SSTL15")),
43 Subsignal("ba", Pins("U5 W4 V7"), IOStandard("SSTL15")),
44 Subsignal("ras_n", Pins("Y9"), IOStandard("SSTL15")),
45 Subsignal("cas_n", Pins("Y7"), IOStandard("SSTL15")),
46 Subsignal("we_n", Pins("V8"), IOStandard("SSTL15")),
47 Subsignal("dm", Pins("M5 L3"), IOStandard("SSTL15")),
49 "N2 M6 P1 N5 P2 N4 R1 P6 "
50 "K3 M2 K4 M3 J6 L5 J4 K6 "
53 Misc("IN_TERM=UNTUNED_SPLIT_50")),
54 Subsignal("dqs_p", Pins("P5 M1"), IOStandard("DIFF_SSTL15")),
55 Subsignal("dqs_n", Pins("P4 L1"), IOStandard("DIFF_SSTL15")),
56 Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15")),
57 Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15")),
58 Subsignal("cke", Pins("Y8"), IOStandard("SSTL15")),
59 Subsignal("odt", Pins("W9"), IOStandard("SSTL15")),
60 Subsignal("reset_n", Pins("AB5"), IOStandard("LVCMOS15")),
61 Subsignal("cs_n", Pins("V9"), IOStandard("SSTL15")),
67 Subsignal("ref_clk", Pins("D17")),
68 IOStandard("LVCMOS33"),
72 Subsignal("rst_n", Pins("F16")),
73 Subsignal("rx_data", Pins("A20 B18")),
74 Subsignal("crs_dv", Pins("C20")),
75 Subsignal("tx_en", Pins("A19")),
76 Subsignal("tx_data", Pins("C18 C19")),
77 Subsignal("mdc", Pins("F14")),
78 Subsignal("mdio", Pins("F13")),
79 Subsignal("rx_er", Pins("B20")),
80 Subsignal("int_n", Pins("D21")),
81 IOStandard("LVCMOS33")
86 Subsignal("data", Pins("L15 L16 K14 M13"), Misc("PULLUP True")),
87 Subsignal("cmd", Pins("L13"), Misc("PULLUP True")),
88 Subsignal("clk", Pins("K18")),
89 IOStandard("LVCMOS33"), Misc("SLEW=FAST")
93 # Platform -----------------------------------------------------------------------------------------
95 class Platform(XilinxPlatform
):
96 default_clk_name
= "clk50"
97 default_clk_period
= 20.0
100 XilinxPlatform
.__init
__(self
, "xc7a35t-fgg484-2", _io
, toolchain
="vivado")