1 # This file is Copyright (c) 2018 Florent Kermarrec <florent@enjoy-digital.fr>
4 from litex
.build
.generic_platform
import *
5 from litex
.build
.xilinx
import XilinxPlatform
, VivadoProgrammer
7 # IOs ----------------------------------------------------------------------------------------------
10 ("user_led", 0, Pins("H17"), IOStandard("LVCMOS33")),
11 ("user_led", 1, Pins("K15"), IOStandard("LVCMOS33")),
12 ("user_led", 2, Pins("J13"), IOStandard("LVCMOS33")),
13 ("user_led", 3, Pins("N14"), IOStandard("LVCMOS33")),
14 ("user_led", 4, Pins("R18"), IOStandard("LVCMOS33")),
15 ("user_led", 5, Pins("V17"), IOStandard("LVCMOS33")),
16 ("user_led", 6, Pins("U17"), IOStandard("LVCMOS33")),
17 ("user_led", 7, Pins("U16"), IOStandard("LVCMOS33")),
18 ("user_led", 8, Pins("V16"), IOStandard("LVCMOS33")),
19 ("user_led", 9, Pins("T15"), IOStandard("LVCMOS33")),
20 ("user_led", 10, Pins("U14"), IOStandard("LVCMOS33")),
21 ("user_led", 11, Pins("T16"), IOStandard("LVCMOS33")),
22 ("user_led", 12, Pins("V15"), IOStandard("LVCMOS33")),
23 ("user_led", 13, Pins("V14"), IOStandard("LVCMOS33")),
24 ("user_led", 14, Pins("V12"), IOStandard("LVCMOS33")),
25 ("user_led", 15, Pins("V11"), IOStandard("LVCMOS33")),
27 ("user_sw", 0, Pins("J15"), IOStandard("LVCMOS33")),
28 ("user_sw", 1, Pins("L16"), IOStandard("LVCMOS33")),
29 ("user_sw", 2, Pins("M13"), IOStandard("LVCMOS33")),
30 ("user_sw", 3, Pins("R15"), IOStandard("LVCMOS33")),
31 ("user_sw", 4, Pins("R17"), IOStandard("LVCMOS33")),
32 ("user_sw", 5, Pins("T18"), IOStandard("LVCMOS33")),
33 ("user_sw", 6, Pins("U18"), IOStandard("LVCMOS33")),
34 ("user_sw", 7, Pins("R13"), IOStandard("LVCMOS33")),
35 ("user_sw", 8, Pins("T8"), IOStandard("LVCMOS33")),
36 ("user_sw", 9, Pins("U8"), IOStandard("LVCMOS33")),
37 ("user_sw", 10, Pins("R16"), IOStandard("LVCMOS33")),
38 ("user_sw", 11, Pins("T13"), IOStandard("LVCMOS33")),
39 ("user_sw", 12, Pins("H6"), IOStandard("LVCMOS33")),
40 ("user_sw", 13, Pins("U12"), IOStandard("LVCMOS33")),
41 ("user_sw", 14, Pins("U11"), IOStandard("LVCMOS33")),
42 ("user_sw", 15, Pins("V10"), IOStandard("LVCMOS33")),
44 ("user_btn", 0, Pins("N17"), IOStandard("LVCMOS33")),
45 ("user_btn", 1, Pins("P18"), IOStandard("LVCMOS33")),
46 ("user_btn", 2, Pins("P17"), IOStandard("LVCMOS33")),
47 ("user_btn", 3, Pins("M17"), IOStandard("LVCMOS33")),
48 ("user_btn", 4, Pins("M18"), IOStandard("LVCMOS33")),
50 ("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
52 ("cpu_reset", 0, Pins("C12"), IOStandard("LVCMOS33")),
55 Subsignal("tx", Pins("D4")),
56 Subsignal("rx", Pins("C4")),
57 IOStandard("LVCMOS33"),
62 "M4 P4 M6 T1 L3 P5 M2 N1",
64 IOStandard("SSTL18_II")),
65 Subsignal("ba", Pins("P2 P3 R1"), IOStandard("SSTL18_II")),
66 Subsignal("ras_n", Pins("N4"), IOStandard("SSTL18_II")),
67 Subsignal("cas_n", Pins("L1"), IOStandard("SSTL18_II")),
68 Subsignal("we_n", Pins("N2"), IOStandard("SSTL18_II")),
69 Subsignal("dm", Pins("T6 U1"), IOStandard("SSTL18_II")),
71 "R7 V6 R8 U7 V7 R6 U6 R5",
72 "T5 U3 V5 U4 V4 T4 V1 T3"),
73 IOStandard("SSTL18_II"),
74 Misc("IN_TERM=UNTUNED_SPLIT_50")),
75 Subsignal("dqs_p", Pins("U9 U2"), IOStandard("DIFF_SSTL18_II")),
76 Subsignal("dqs_n", Pins("V9 V2"), IOStandard("DIFF_SSTL18_II")),
77 Subsignal("clk_p", Pins("L6"), IOStandard("DIFF_SSTL18_II")),
78 Subsignal("clk_n", Pins("L5"), IOStandard("DIFF_SSTL18_II")),
79 Subsignal("cke", Pins("M1"), IOStandard("SSTL18_II")),
80 Subsignal("odt", Pins("M3"), IOStandard("SSTL18_II")),
81 Subsignal("cs_n", Pins("K6"), IOStandard("SSTL18_II")),
86 Subsignal("ref_clk", Pins("D5")),
87 IOStandard("LVCMOS33"),
91 Subsignal("rst_n", Pins("B3")),
92 Subsignal("rx_data", Pins("C11 D10")),
93 Subsignal("crs_dv", Pins("D9")),
94 Subsignal("tx_en", Pins("B9")),
95 Subsignal("tx_data", Pins("A10 A8")),
96 Subsignal("mdc", Pins("C9")),
97 Subsignal("mdio", Pins("A9")),
98 Subsignal("rx_er", Pins("C10")),
99 Subsignal("int_n", Pins("D8")),
100 IOStandard("LVCMOS33")
104 # Platform -----------------------------------------------------------------------------------------
106 class Platform(XilinxPlatform
):
107 default_clk_name
= "clk100"
108 default_clk_period
= 10.0
111 XilinxPlatform
.__init
__(self
, "xc7a100t-CSG324-1", _io
, toolchain
="vivado")
112 self
.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
114 def create_programmer(self
):
115 return VivadoProgrammer()
117 def do_finalize(self
, fragment
):
118 XilinxPlatform
.do_finalize(self
, fragment
)