litex/boards/platforms/nexys_video.py

   1 # This file is Copyright (c) 2015 Florent Kermarrec <florent@enjoy-digital.fr>
   2 # License: BSD
   3
   4 from litex.build.generic_platform import *
   5 from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
   6
   7 _io = [
   8     ("user_led", 0, Pins("T14"), IOStandard("LVCMOS25")),
   9     ("user_led", 1, Pins("T15"), IOStandard("LVCMOS25")),
  10     ("user_led", 2, Pins("T16"), IOStandard("LVCMOS25")),
  11     ("user_led", 3, Pins("U16"), IOStandard("LVCMOS25")),
  12     ("user_led", 4, Pins("V15"), IOStandard("LVCMOS25")),
  13     ("user_led", 5, Pins("W16"), IOStandard("LVCMOS25")),
  14     ("user_led", 6, Pins("W15"), IOStandard("LVCMOS25")),
  15     ("user_led", 7, Pins("Y13"), IOStandard("LVCMOS25")),
  16
  17     ("user_sw", 0, Pins("E22"), IOStandard("LVCMOS25")),
  18     ("user_sw", 1, Pins("F21"), IOStandard("LVCMOS25")),
  19     ("user_sw", 2, Pins("G21"), IOStandard("LVCMOS25")),
  20     ("user_sw", 3, Pins("G22"), IOStandard("LVCMOS25")),
  21     ("user_sw", 4, Pins("H17"), IOStandard("LVCMOS25")),
  22     ("user_sw", 5, Pins("J16"), IOStandard("LVCMOS25")),
  23     ("user_sw", 6, Pins("K13"), IOStandard("LVCMOS25")),
  24     ("user_sw", 7, Pins("M17"), IOStandard("LVCMOS25")),
  25
  26
  27     ("user_btn", 0, Pins("B22"), IOStandard("LVCMOS25")),
  28     ("user_btn", 1, Pins("D22"), IOStandard("LVCMOS25")),
  29     ("user_btn", 2, Pins("C22"), IOStandard("LVCMOS25")),
  30     ("user_btn", 3, Pins("D14"), IOStandard("LVCMOS25")),
  31     ("user_btn", 4, Pins("F15"), IOStandard("LVCMOS25")),
  32     ("user_btn", 5, Pins("G4"),  IOStandard("LVCMOS25")),
  33
  34     ("vadj", 0, Pins("AA13 AB17"), IOStandard("LVCMOS25")),
  35
  36     ("oled", 0,
  37         Subsignal("dc",   Pins("W22")),
  38         Subsignal("res",  Pins("U21")),
  39         Subsignal("sclk", Pins("W21")),
  40         Subsignal("sdin", Pins("Y22")),
  41         Subsignal("vbat", Pins("P20")),
  42         Subsignal("vdd",  Pins("V22")),
  43         IOStandard("LVCMOS33")
  44     ),
  45
  46     ("clk100", 0, Pins("R4"), IOStandard("LVCMOS33")),
  47
  48     ("cpu_reset", 0, Pins("G4"), IOStandard("LVCMOS15")),
  49
  50     ("serial", 0,
  51         Subsignal("tx", Pins("AA19")),
  52         Subsignal("rx", Pins("V18")),
  53         IOStandard("LVCMOS33"),
  54     ),
  55
  56     ("ddram", 0,
  57         Subsignal("a", Pins(
  58             "M2 M5 M3 M1 L6 P1 N3 N2",
  59             "M6 R1 L5 N5 N4 P2 P6"),
  60             IOStandard("SSTL15")),
  61         Subsignal("ba", Pins("L3 K6 L4"), IOStandard("SSTL15")),
  62         Subsignal("ras_n", Pins("J4"), IOStandard("SSTL15")),
  63         Subsignal("cas_n", Pins("K3"), IOStandard("SSTL15")),
  64         Subsignal("we_n", Pins("L1"), IOStandard("SSTL15")),
  65         Subsignal("dm", Pins("G3 F1"), IOStandard("SSTL15")),
  66         Subsignal("dq", Pins(
  67             "G2 H4 H5 J1 K1 H3 H2 J5",
  68             "E3 B2 F3 D2 C2 A1 E2 B1"),
  69             IOStandard("SSTL15"),
  70             Misc("IN_TERM=UNTUNED_SPLIT_50")),
  71         Subsignal("dqs_p", Pins("K2 E1"), IOStandard("DIFF_SSTL15")),
  72         Subsignal("dqs_n", Pins("J2 D1"), IOStandard("DIFF_SSTL15")),
  73         Subsignal("clk_p", Pins("P5"), IOStandard("DIFF_SSTL15")),
  74         Subsignal("clk_n", Pins("P4"), IOStandard("DIFF_SSTL15")),
  75         Subsignal("cke", Pins("J6"), IOStandard("SSTL15")),
  76         Subsignal("odt", Pins("K4"), IOStandard("SSTL15")),
  77         Subsignal("reset_n", Pins("G1"), IOStandard("SSTL15")),
  78         Misc("SLEW=FAST"),
  79     ),
  80
  81     ("eth_clocks", 0,
  82         Subsignal("tx", Pins("AA14")),
  83         Subsignal("rx", Pins("V13")),
  84         IOStandard("LVCMOS25")
  85     ),
  86     ("eth", 0,
  87         Subsignal("rst_n", Pins("U7"), IOStandard("LVCMOS33")),
  88         Subsignal("int_n", Pins("Y14")),
  89         Subsignal("mdio", Pins("Y16")),
  90         Subsignal("mdc", Pins("AA16")),
  91         Subsignal("rx_ctl", Pins("W10")),
  92         Subsignal("rx_data", Pins("AB16 AA15 AB15 AB11")),
  93         Subsignal("tx_ctl", Pins("V10")),
  94         Subsignal("tx_data", Pins("Y12 W12 W11 Y11")),
  95         IOStandard("LVCMOS25")
  96     ),
  97
  98     ("hdmi_in", 0,
  99         Subsignal("clk_p", Pins("V4"), IOStandard("TMDS_33")),
 100         Subsignal("clk_n", Pins("W4"), IOStandard("TMDS_33")),
 101         Subsignal("data0_p", Pins("Y3"), IOStandard("TMDS_33")),
 102         Subsignal("data0_n", Pins("AA3"), IOStandard("TMDS_33")),
 103         Subsignal("data1_p", Pins("W2"), IOStandard("TMDS_33")),
 104         Subsignal("data1_n", Pins("Y2"), IOStandard("TMDS_33")),
 105         Subsignal("data2_p", Pins("U2"), IOStandard("TMDS_33")),
 106         Subsignal("data2_n", Pins("V2"), IOStandard("TMDS_33")),
 107         Subsignal("scl", Pins("Y4"), IOStandard("LVCMOS33")),
 108         Subsignal("sda", Pins("AB5"), IOStandard("LVCMOS33")),
 109         Subsignal("hpd_en", Pins("AB12"), IOStandard("LVCMOS25")),
 110         Subsignal("cec", Pins("AA5"), IOStandard("LVCMOS33")),  # FIXME
 111         Subsignal("txen", Pins("R3"), IOStandard("LVCMOS33")),  # FIXME
 112     ),
 113
 114     ("hdmi_out", 0,
 115         Subsignal("clk_p", Pins("T1"), IOStandard("TMDS_33")),
 116         Subsignal("clk_n", Pins("U1"), IOStandard("TMDS_33")),
 117         Subsignal("data0_p", Pins("W1"), IOStandard("TMDS_33")),
 118         Subsignal("data0_n", Pins("Y1"), IOStandard("TMDS_33")),
 119         Subsignal("data1_p", Pins("AA1"), IOStandard("TMDS_33")),
 120         Subsignal("data1_n", Pins("AB1"), IOStandard("TMDS_33")),
 121         Subsignal("data2_p", Pins("AB3"), IOStandard("TMDS_33")),
 122         Subsignal("data2_n", Pins("AB2"), IOStandard("TMDS_33")),
 123         Subsignal("scl", Pins("U3"), IOStandard("LVCMOS33")),
 124         Subsignal("sda", Pins("V3"), IOStandard("LVCMOS33")),
 125         Subsignal("cec", Pins("AA4"), IOStandard("LVCMOS33")),  # FIXME
 126         Subsignal("hdp", Pins("AB13"), IOStandard("LVCMOS25")), # FIXME
 127     ),
 128 ]
 129
 130 _connectors = [
 131     ("LPC", {
 132         "GBTCLK0_M2C_P": "F10",
 133         "GBTCLK0_M2C_N": "E10",
 134         "LA01_CC_P": "J20",
 135         "LA01_CC_N": "J21",
 136         "LA05_P": "M21",
 137         "LA05_N": "L21",
 138         "LA09_P": "H20",
 139         "LA09_N": "G20",
 140         "LA13_P": "K17",
 141         "LA13_N": "J17",
 142         "LA17_CC_P": "B17",
 143         "LA17_CC_N": "B18",
 144         "LA23_P": "B21",
 145         "LA23_N": "A21",
 146         "LA26_P": "F18",
 147         "LA26_N": "E18",
 148         "CLK0_M2C_P": "J19",
 149         "CLK0_M2C_N": "A19",
 150         "LA02_P": "M18",
 151         "LA02_N": "L18",
 152         "LA04_P": "N20",
 153         "LA04_N": "M20",
 154         "LA07_P": "M13",
 155         "LA07_N": "L13",
 156         "LA11_P": "L14",
 157         "LA11_N": "L15",
 158         "LA15_P": "L16",
 159         "LA15_N": "K16",
 160         "LA19_P": "A18",
 161         "LA19_N": "A19",
 162         "LA21_P": "E19",
 163         "LA21_N": "D19",
 164         "LA24_P": "B15",
 165         "LA24_N": "B16",
 166         "LA28_P": "C13",
 167         "LA28_N": "B13",
 168         "LA30_P": "A13",
 169         "LA30_N": "A14",
 170         "LA32_P": "A15",
 171         "LA32_N": "A16",
 172         "LA06_P": "N22",
 173         "LA06_N": "M22",
 174         "LA10_P": "K21",
 175         "LA10_N": "K22",
 176         "LA14_P": "J22",
 177         "LA14_N": "H22",
 178         "LA18_CC_P": "D17",
 179         "LA18_CC_N": "C17",
 180         "LA27_P": "B20",
 181         "LA27_N": "A20",
 182         "CLK1_M2C_P": "C18",
 183         "CLK1_M2C_N": "C19",
 184         "LA00_CC_P": "K18",
 185         "LA00_CC_N": "K19",
 186         "LA03_P": "N18",
 187         "LA03_N": "N19",
 188         "LA08_P": "M15",
 189         "LA08_N": "M16",
 190         "LA12_P": "L19",
 191         "LA12_N": "L20",
 192         "LA16_P": "G17",
 193         "LA16_N": "G18",
 194         "LA20_P": "F19",
 195         "LA20_N": "F20",
 196         "LA22_P": "E21",
 197         "LA22_N": "D21",
 198         "LA25_P": "F16",
 199         "LA25_N": "E17",
 200         "LA29_P": "C14",
 201         "LA29_N": "C15",
 202         "LA31_P": "E13",
 203         "LA31_N": "E14",
 204         "LA33_P": "F13",
 205         "LA33_N": "F14",
 206         }
 207     )
 208 ]
 209
 210 class Platform(XilinxPlatform):
 211     default_clk_name = "clk100"
 212     default_clk_period = 10.0
 213
 214     def __init__(self, toolchain="vivado", programmer="vivado"):
 215         XilinxPlatform.__init__(self, "xc7a200t-sbg484-1", _io, _connectors,
 216                                 toolchain=toolchain)
 217         self.toolchain.bitstream_commands = \
 218             ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
 219         self.toolchain.additional_commands = \
 220             ["write_cfgmem -force -format bin -interface spix4 -size 16 "
 221              "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
 222         self.programmer = programmer
 223         self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
 224
 225
 226     def create_programmer(self):
 227         if self.programmer == "xc3sprog":
 228             return XC3SProg("nexys4")
 229         elif self.programmer == "vivado":
 230             return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
 231         else:
 232             raise ValueError("{} programmer is not supported"
 233                              .format(self.programmer))
 234
 235     def do_finalize(self, fragment):
 236         XilinxPlatform.do_finalize(self, fragment)
 237         try:
 238             self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
 239         except ConstraintError:
 240             pass