1 # This file is Copyright (c) 2015 Florent Kermarrec <florent@enjoy-digital.fr>
4 from litex
.build
.generic_platform
import *
5 from litex
.build
.xilinx
import XilinxPlatform
, XC3SProg
, VivadoProgrammer
8 ("user_led", 0, Pins("T14"), IOStandard("LVCMOS25")),
9 ("user_led", 1, Pins("T15"), IOStandard("LVCMOS25")),
10 ("user_led", 2, Pins("T16"), IOStandard("LVCMOS25")),
11 ("user_led", 3, Pins("U16"), IOStandard("LVCMOS25")),
12 ("user_led", 4, Pins("V15"), IOStandard("LVCMOS25")),
13 ("user_led", 5, Pins("W16"), IOStandard("LVCMOS25")),
14 ("user_led", 6, Pins("W15"), IOStandard("LVCMOS25")),
15 ("user_led", 7, Pins("Y13"), IOStandard("LVCMOS25")),
17 ("user_sw", 0, Pins("E22"), IOStandard("LVCMOS12")),
18 ("user_sw", 1, Pins("F21"), IOStandard("LVCMOS12")),
19 ("user_sw", 2, Pins("G21"), IOStandard("LVCMOS12")),
20 ("user_sw", 3, Pins("G22"), IOStandard("LVCMOS12")),
21 ("user_sw", 4, Pins("H17"), IOStandard("LVCMOS12")),
22 ("user_sw", 5, Pins("J16"), IOStandard("LVCMOS12")),
23 ("user_sw", 6, Pins("K13"), IOStandard("LVCMOS12")),
24 ("user_sw", 7, Pins("M17"), IOStandard("LVCMOS12")),
27 ("user_btn", 0, Pins("B22"), IOStandard("LVCMOS12")),
28 ("user_btn", 1, Pins("D22"), IOStandard("LVCMOS12")),
29 ("user_btn", 2, Pins("C22"), IOStandard("LVCMOS12")),
30 ("user_btn", 3, Pins("D14"), IOStandard("LVCMOS12")),
31 ("user_btn", 4, Pins("F15"), IOStandard("LVCMOS12")),
32 ("user_btn", 5, Pins("G4"), IOStandard("LVCMOS12")),
35 Subsignal("dc", Pins("W22")),
36 Subsignal("res", Pins("U21")),
37 Subsignal("sclk", Pins("W21")),
38 Subsignal("sdin", Pins("Y22")),
39 Subsignal("vbat", Pins("P20")),
40 Subsignal("vdd", Pins("V22")),
41 IOStandard("LVCMOS33")
44 ("clk100", 0, Pins("R4"), IOStandard("LVCMOS33")),
46 ("cpu_reset", 0, Pins("G4"), IOStandard("LVCMOS15")),
49 Subsignal("tx", Pins("AA19")),
50 Subsignal("rx", Pins("V18")),
51 IOStandard("LVCMOS33"),
56 "M2 M5 M3 M1 L6 P1 N3 N2",
57 "M6 R1 L5 N5 N4 P2 P6"),
58 IOStandard("SSTL15")),
59 Subsignal("ba", Pins("L3 K6 L4"), IOStandard("SSTL15")),
60 Subsignal("ras_n", Pins("J4"), IOStandard("SSTL15")),
61 Subsignal("cas_n", Pins("K3"), IOStandard("SSTL15")),
62 Subsignal("we_n", Pins("L1"), IOStandard("SSTL15")),
63 Subsignal("dm", Pins("G3 F1"), IOStandard("SSTL15")),
65 "G2 H4 H5 J1 K1 H3 H2 J5",
66 "E3 B2 F3 D2 C2 A1 E2 B1"),
68 Misc("IN_TERM=UNTUNED_SPLIT_50")),
69 Subsignal("dqs_p", Pins("K2 E1"), IOStandard("DIFF_SSTL15")),
70 Subsignal("dqs_n", Pins("J2 D1"), IOStandard("DIFF_SSTL15")),
71 Subsignal("clk_p", Pins("P5"), IOStandard("DIFF_SSTL15")),
72 Subsignal("clk_n", Pins("P4"), IOStandard("DIFF_SSTL15")),
73 Subsignal("cke", Pins("J6"), IOStandard("SSTL15")),
74 Subsignal("odt", Pins("K4"), IOStandard("SSTL15")),
75 Subsignal("reset_n", Pins("G1"), IOStandard("SSTL15")),
80 Subsignal("tx", Pins("AA14")),
81 Subsignal("rx", Pins("V13")),
82 IOStandard("LVCMOS25")
85 Subsignal("rst_n", Pins("U7"), IOStandard("LVCMOS33")),
86 Subsignal("int_n", Pins("Y14")),
87 Subsignal("mdio", Pins("Y16")),
88 Subsignal("mdc", Pins("AA16")),
89 Subsignal("rx_ctl", Pins("W10")),
90 Subsignal("rx_data", Pins("AB16 AA15 AB15 AB11")),
91 Subsignal("tx_ctl", Pins("V10")),
92 Subsignal("tx_data", Pins("Y12 W12 W11 Y11")),
93 IOStandard("LVCMOS25")
97 Subsignal("clk_p", Pins("V4"), IOStandard("TDMS")),
98 Subsignal("clk_n", Pins("W4"), IOStandard("TDMS")),
99 Subsignal("data0_p", Pins("Y3"), IOStandard("TDMS")),
100 Subsignal("data0_n", Pins("AA3"), IOStandard("TDMS")),
101 Subsignal("data1_p", Pins("W2"), IOStandard("TDMS")),
102 Subsignal("data1_n", Pins("Y2"), IOStandard("TDMS")),
103 Subsignal("data2_p", Pins("U2"), IOStandard("TDMS")),
104 Subsignal("data2_n", Pins("V2"), IOStandard("TDMS")),
105 Subsignal("scl", Pins("Y4"), IOStandard("LVCMOS33")),
106 Subsignal("sda", Pins("AB5"), IOStandard("LVCMOS33")),
107 Subsignal("cec", Pins("AA5"), IOStandard("LVCMOS33")), # FIXME
108 Subsignal("txen", Pins("R3"), IOStandard("LVCMOS33")), # FIXME
109 Subsignal("hpa", Pins("AB12"), IOStandard("LVCMOS33")), # FIXME
113 Subsignal("clk_p", Pins("T1"), IOStandard("TMDS")),
114 Subsignal("clk_n", Pins("U1"), IOStandard("TMDS")),
115 Subsignal("data0_p", Pins("W1"), IOStandard("TMDS")),
116 Subsignal("data0_n", Pins("Y1"), IOStandard("TMDS")),
117 Subsignal("data1_p", Pins("AB1"), IOStandard("TMDS")),
118 Subsignal("data1_n", Pins("AA1"), IOStandard("TMDS")),
119 Subsignal("data2_p", Pins("AB2"), IOStandard("TMDS")),
120 Subsignal("data2_n", Pins("AB3"), IOStandard("TMDS")),
121 Subsignal("scl", Pins("U3"), IOStandard("LVCMOS33")),
122 Subsignal("sda", Pins("V3"), IOStandard("LVCMOS33")),
123 Subsignal("cec", Pins("AA4"), IOStandard("LVCMOS33")), # FIXME
124 Subsignal("hdp", Pins("AB13"), IOStandard("LVCMOS25")), # FIXME
129 class Platform(XilinxPlatform
):
130 default_clk_name
= "clk100"
131 default_clk_period
= 10.0
133 def __init__(self
, toolchain
="vivado", programmer
="vivado"):
134 XilinxPlatform
.__init
__(self
, "xc7a200t-sbg484-1", _io
,
136 self
.toolchain
.bitstream_commands
= \
137 ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
138 self
.toolchain
.additional_commands
= \
139 ["write_cfgmem -force -format bin -interface spix4 -size 16 "
140 "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
141 self
.programmer
= programmer
142 self
.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
145 def create_programmer(self
):
146 if self
.programmer
== "xc3sprog":
147 return XC3SProg("nexys4")
148 elif self
.programmer
== "vivado":
149 return VivadoProgrammer(flash_part
="n25q128-3.3v-spi-x1_x2_x4")
151 raise ValueError("{} programmer is not supported"
152 .format(self
.programmer
))
154 def do_finalize(self
, fragment
):
155 XilinxPlatform
.do_finalize(self
, fragment
)
157 self
.add_period_constraint(self
.lookup_request("eth_clocks").rx
, 8.0)
158 except ConstraintError
: