litex/boards/platforms/nexys_video.py

   1 # This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   2 # License: BSD
   3
   4 from litex.build.generic_platform import *
   5 from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
   6 from litex.build.openocd import OpenOCD
   7
   8 # IOs ----------------------------------------------------------------------------------------------
   9
  10 _io = [
  11     ("clk100", 0, Pins("R4"), IOStandard("LVCMOS33")),
  12
  13     ("cpu_reset", 0, Pins("G4"), IOStandard("LVCMOS15")),
  14
  15     ("user_led", 0, Pins("T14"), IOStandard("LVCMOS25")),
  16     ("user_led", 1, Pins("T15"), IOStandard("LVCMOS25")),
  17     ("user_led", 2, Pins("T16"), IOStandard("LVCMOS25")),
  18     ("user_led", 3, Pins("U16"), IOStandard("LVCMOS25")),
  19     ("user_led", 4, Pins("V15"), IOStandard("LVCMOS25")),
  20     ("user_led", 5, Pins("W16"), IOStandard("LVCMOS25")),
  21     ("user_led", 6, Pins("W15"), IOStandard("LVCMOS25")),
  22     ("user_led", 7, Pins("Y13"), IOStandard("LVCMOS25")),
  23
  24     ("user_sw", 0, Pins("E22"), IOStandard("LVCMOS25")),
  25     ("user_sw", 1, Pins("F21"), IOStandard("LVCMOS25")),
  26     ("user_sw", 2, Pins("G21"), IOStandard("LVCMOS25")),
  27     ("user_sw", 3, Pins("G22"), IOStandard("LVCMOS25")),
  28     ("user_sw", 4, Pins("H17"), IOStandard("LVCMOS25")),
  29     ("user_sw", 5, Pins("J16"), IOStandard("LVCMOS25")),
  30     ("user_sw", 6, Pins("K13"), IOStandard("LVCMOS25")),
  31     ("user_sw", 7, Pins("M17"), IOStandard("LVCMOS25")),
  32
  33
  34     ("user_btn", 0, Pins("B22"), IOStandard("LVCMOS25")),
  35     ("user_btn", 1, Pins("D22"), IOStandard("LVCMOS25")),
  36     ("user_btn", 2, Pins("C22"), IOStandard("LVCMOS25")),
  37     ("user_btn", 3, Pins("D14"), IOStandard("LVCMOS25")),
  38     ("user_btn", 4, Pins("F15"), IOStandard("LVCMOS25")),
  39     ("user_btn", 5, Pins("G4"),  IOStandard("LVCMOS25")),
  40
  41     ("vadj", 0, Pins("AA13 AB17"), IOStandard("LVCMOS25")),
  42
  43     ("oled", 0,
  44         Subsignal("dc",   Pins("W22")),
  45         Subsignal("res",  Pins("U21")),
  46         Subsignal("sclk", Pins("W21")),
  47         Subsignal("sdin", Pins("Y22")),
  48         Subsignal("vbat", Pins("P20")),
  49         Subsignal("vdd",  Pins("V22")),
  50         IOStandard("LVCMOS33")
  51     ),
  52
  53     ("serial", 0,
  54         Subsignal("tx", Pins("AA19")),
  55         Subsignal("rx", Pins("V18")),
  56         IOStandard("LVCMOS33"),
  57     ),
  58
  59     ("usb_fifo", 0, # Can be used when FT2232H's Channel A configured to ASYNC FIFO 245 mode
  60         Subsignal("data",  Pins("U20 P14 P15 U17 R17 P16 R18 N14")),
  61         Subsignal("rxf_n", Pins("N17")),
  62         Subsignal("txe_n", Pins("Y19")),
  63         Subsignal("rd_n",  Pins("P19")),
  64         Subsignal("wr_n",  Pins("R19")),
  65         Subsignal("siwua", Pins("P17")),
  66         Subsignal("oe_n",  Pins("V17")),
  67         Misc("SLEW=FAST"),
  68         Drive(8),
  69         IOStandard("LVCMOS33"),
  70     ),
  71
  72     ("spisdcard", 0,
  73         Subsignal("rst",  Pins("V20")),
  74         Subsignal("clk",  Pins("W19")),
  75         Subsignal("mosi", Pins("W20"), Misc("PULLUP True")),
  76         Subsignal("cs_n", Pins("U18"), Misc("PULLUP True")),
  77         Subsignal("miso", Pins("V19"), Misc("PULLUP True")),
  78         Misc("SLEW=FAST"),
  79         IOStandard("LVCMOS33"),
  80     ),
  81
  82     ("sdcard", 0,
  83         Subsignal("rst",  Pins("V20"),             Misc("PULLUP True")),
  84         Subsignal("data", Pins("V19 T21 T20 U18"), Misc("PULLUP True")),
  85         Subsignal("cmd",  Pins("W20"),             Misc("PULLUP True")),
  86         Subsignal("clk",  Pins("W19")),
  87         Misc("SLEW=FAST"),
  88         IOStandard("LVCMOS33"),
  89     ),
  90
  91     ("ddram", 0,
  92         Subsignal("a", Pins(
  93             "M2 M5 M3 M1 L6 P1 N3 N2",
  94             "M6 R1 L5 N5 N4 P2 P6"),
  95             IOStandard("SSTL15")),
  96         Subsignal("ba",    Pins("L3 K6 L4"), IOStandard("SSTL15")),
  97         Subsignal("ras_n", Pins("J4"), IOStandard("SSTL15")),
  98         Subsignal("cas_n", Pins("K3"), IOStandard("SSTL15")),
  99         Subsignal("we_n",  Pins("L1"), IOStandard("SSTL15")),
 100         Subsignal("dm", Pins("G3 F1"), IOStandard("SSTL15")),
 101         Subsignal("dq", Pins(
 102             "G2 H4 H5 J1 K1 H3 H2 J5",
 103             "E3 B2 F3 D2 C2 A1 E2 B1"),
 104             IOStandard("SSTL15"),
 105             Misc("IN_TERM=UNTUNED_SPLIT_50")),
 106         Subsignal("dqs_p", Pins("K2 E1"), IOStandard("DIFF_SSTL15")),
 107         Subsignal("dqs_n", Pins("J2 D1"), IOStandard("DIFF_SSTL15")),
 108         Subsignal("clk_p", Pins("P5"),    IOStandard("DIFF_SSTL15")),
 109         Subsignal("clk_n", Pins("P4"),    IOStandard("DIFF_SSTL15")),
 110         Subsignal("cke",   Pins("J6"),    IOStandard("SSTL15")),
 111         Subsignal("odt",   Pins("K4"),    IOStandard("SSTL15")),
 112         Subsignal("reset_n", Pins("G1"), IOStandard("SSTL15")),
 113         Misc("SLEW=FAST"),
 114     ),
 115
 116     ("eth_clocks", 0,
 117         Subsignal("tx", Pins("AA14")),
 118         Subsignal("rx", Pins("V13")),
 119         IOStandard("LVCMOS25")
 120     ),
 121     ("eth", 0,
 122         Subsignal("rst_n",   Pins("U7"), IOStandard("LVCMOS33")),
 123         Subsignal("int_n",   Pins("Y14")),
 124         Subsignal("mdio",    Pins("Y16")),
 125         Subsignal("mdc",     Pins("AA16")),
 126         Subsignal("rx_ctl",  Pins("W10")),
 127         Subsignal("rx_data", Pins("AB16 AA15 AB15 AB11")),
 128         Subsignal("tx_ctl",  Pins("V10")),
 129         Subsignal("tx_data", Pins("Y12 W12 W11 Y11")),
 130         IOStandard("LVCMOS25")
 131     ),
 132
 133     ("hdmi_in", 0,
 134         Subsignal("clk_p",   Pins("V4"),   IOStandard("TMDS_33")),
 135         Subsignal("clk_n",   Pins("W4"),   IOStandard("TMDS_33")),
 136         Subsignal("data0_p", Pins("Y3"),   IOStandard("TMDS_33")),
 137         Subsignal("data0_n", Pins("AA3"),  IOStandard("TMDS_33")),
 138         Subsignal("data1_p", Pins("W2"),   IOStandard("TMDS_33")),
 139         Subsignal("data1_n", Pins("Y2"),   IOStandard("TMDS_33")),
 140         Subsignal("data2_p", Pins("U2"),   IOStandard("TMDS_33")),
 141         Subsignal("data2_n", Pins("V2"),   IOStandard("TMDS_33")),
 142         Subsignal("scl",     Pins("Y4"),   IOStandard("LVCMOS33")),
 143         Subsignal("sda",     Pins("AB5"),  IOStandard("LVCMOS33")),
 144         Subsignal("hpd_en",  Pins("AB12"), IOStandard("LVCMOS25")),
 145         Subsignal("cec",     Pins("AA5"),  IOStandard("LVCMOS33")), # FIXME
 146         Subsignal("txen",    Pins("R3"),   IOStandard("LVCMOS33")), # FIXME
 147     ),
 148
 149     ("hdmi_out", 0,
 150         Subsignal("clk_p",   Pins("T1"),   IOStandard("TMDS_33")),
 151         Subsignal("clk_n",   Pins("U1"),   IOStandard("TMDS_33")),
 152         Subsignal("data0_p", Pins("W1"),   IOStandard("TMDS_33")),
 153         Subsignal("data0_n", Pins("Y1"),   IOStandard("TMDS_33")),
 154         Subsignal("data1_p", Pins("AA1"),  IOStandard("TMDS_33")),
 155         Subsignal("data1_n", Pins("AB1"),  IOStandard("TMDS_33")),
 156         Subsignal("data2_p", Pins("AB3"),  IOStandard("TMDS_33")),
 157         Subsignal("data2_n", Pins("AB2"),  IOStandard("TMDS_33")),
 158         Subsignal("scl",     Pins("U3"),   IOStandard("LVCMOS33")),
 159         Subsignal("sda",     Pins("V3"),   IOStandard("LVCMOS33")),
 160         Subsignal("cec",     Pins("AA4"),  IOStandard("LVCMOS33")), # FIXME
 161         Subsignal("hdp",     Pins("AB13"), IOStandard("LVCMOS25")), # FIXME
 162     ),
 163 ]
 164
 165 # Connectors ---------------------------------------------------------------------------------------
 166
 167 _connectors = [
 168     ("LPC", {
 169         "DP0_C2M_P"     : "D7",
 170         "DP0_C2M_N"     : "C7",
 171         "DP0_M2C_P"     : "D9",
 172         "DP0_M2C_N"     : "C9",
 173         "GBTCLK0_M2C_P" : "F10",
 174         "GBTCLK0_M2C_N" : "E10",
 175         "LA01_CC_P"     : "J20",
 176         "LA01_CC_N"     : "J21",
 177         "LA05_P"        : "M21",
 178         "LA05_N"        : "L21",
 179         "LA09_P"        : "H20",
 180         "LA09_N"        : "G20",
 181         "LA13_P"        : "K17",
 182         "LA13_N"        : "J17",
 183         "LA17_CC_P"     : "B17",
 184         "LA17_CC_N"     : "B18",
 185         "LA23_P"        : "B21",
 186         "LA23_N"        : "A21",
 187         "LA26_P"        : "F18",
 188         "LA26_N"        : "E18",
 189         "CLK0_M2C_P"    : "J19",
 190         "CLK0_M2C_N"    : "A19",
 191         "LA02_P"        : "M18",
 192         "LA02_N"        : "L18",
 193         "LA04_P"        : "N20",
 194         "LA04_N"        : "M20",
 195         "LA07_P"        : "M13",
 196         "LA07_N"        : "L13",
 197         "LA11_P"        : "L14",
 198         "LA11_N"        : "L15",
 199         "LA15_P"        : "L16",
 200         "LA15_N"        : "K16",
 201         "LA19_P"        : "A18",
 202         "LA19_N"        : "A19",
 203         "LA21_P"        : "E19",
 204         "LA21_N"        : "D19",
 205         "LA24_P"        : "B15",
 206         "LA24_N"        : "B16",
 207         "LA28_P"        : "C13",
 208         "LA28_N"        : "B13",
 209         "LA30_P"        : "A13",
 210         "LA30_N"        : "A14",
 211         "LA32_P"        : "A15",
 212         "LA32_N"        : "A16",
 213         "LA06_P"        : "N22",
 214         "LA06_N"        : "M22",
 215         "LA10_P"        : "K21",
 216         "LA10_N"        : "K22",
 217         "LA14_P"        : "J22",
 218         "LA14_N"        : "H22",
 219         "LA18_CC_P"     : "D17",
 220         "LA18_CC_N"     : "C17",
 221         "LA27_P"        : "B20",
 222         "LA27_N"        : "A20",
 223         "CLK1_M2C_P"    : "C18",
 224         "CLK1_M2C_N"    : "C19",
 225         "LA00_CC_P"     : "K18",
 226         "LA00_CC_N"     : "K19",
 227         "LA03_P"        : "N18",
 228         "LA03_N"        : "N19",
 229         "LA08_P"        : "M15",
 230         "LA08_N"        : "M16",
 231         "LA12_P"        : "L19",
 232         "LA12_N"        : "L20",
 233         "LA16_P"        : "G17",
 234         "LA16_N"        : "G18",
 235         "LA20_P"        : "F19",
 236         "LA20_N"        : "F20",
 237         "LA22_P"        : "E21",
 238         "LA22_N"        : "D21",
 239         "LA25_P"        : "F16",
 240         "LA25_N"        : "E17",
 241         "LA29_P"        : "C14",
 242         "LA29_N"        : "C15",
 243         "LA31_P"        : "E13",
 244         "LA31_N"        : "E14",
 245         "LA33_P"        : "F13",
 246         "LA33_N"        : "F14",
 247         }
 248     )
 249 ]
 250
 251 # Platform -----------------------------------------------------------------------------------------
 252
 253 class Platform(XilinxPlatform):
 254     default_clk_name   = "clk100"
 255     default_clk_period = 1e9/100e6
 256
 257     def __init__(self):
 258         XilinxPlatform.__init__(self, "xc7a200t-sbg484-1", _io, _connectors, toolchain="vivado")
 259         self.toolchain.bitstream_commands = \
 260             ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
 261         self.toolchain.additional_commands = \
 262             ["write_cfgmem -force -format bin -interface spix4 -size 16 "
 263              "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
 264         self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
 265
 266     def create_programmer(self):
 267         return OpenOCD("openocd_nexys_video.cfg", "bscan_spi_xc7a200t.bit")
 268
 269     def do_finalize(self, fragment):
 270         XilinxPlatform.do_finalize(self, fragment)
 271         try:
 272             self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
 273         except ConstraintError:
 274             pass
 275
 276     def do_finalize(self, fragment):
 277         XilinxPlatform.do_finalize(self, fragment)
 278         self.add_period_constraint(self.lookup_request("clk100",        loose=True), 1e9/100e6)
 279         self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6)