litex/boards/platforms/versa.py

   1 # This file is Copyright (c) 2013 Florent Kermarrec <florent@enjoy-digital.fr>
   2 # License: BSD
   3
   4 from litex.build.generic_platform import *
   5 from litex.build.lattice import LatticePlatform
   6 from litex.build.lattice.programmer import LatticeProgrammer
   7
   8
   9 _io = [
  10     ("clk100", 0, Pins("L5"), IOStandard("LVDS25")),
  11     ("rst_n", 0, Pins("A21"), IOStandard("LVCMOS33")),
  12
  13     ("user_led", 0, Pins("Y20"), IOStandard("LVCMOS33")),
  14     ("user_led", 1, Pins("AA21"), IOStandard("LVCMOS33")),
  15     ("user_led", 2, Pins("U18"), IOStandard("LVCMOS33")),
  16     ("user_led", 3, Pins("U19"), IOStandard("LVCMOS33")),
  17     ("user_led", 4, Pins("W19"), IOStandard("LVCMOS33")),
  18     ("user_led", 5, Pins("V19"), IOStandard("LVCMOS33")),
  19     ("user_led", 6, Pins("AB20"), IOStandard("LVCMOS33")),
  20     ("user_led", 7, Pins("AA20"), IOStandard("LVCMOS33")),
  21
  22     ("user_dip_btn", 0, Pins("J7"), IOStandard("LVCMOS15")),
  23     ("user_dip_btn", 1, Pins("J6"), IOStandard("LVCMOS15")),
  24     ("user_dip_btn", 2, Pins("H2"), IOStandard("LVCMOS15")),
  25     ("user_dip_btn", 3, Pins("H3"), IOStandard("LVCMOS15")),
  26     ("user_dip_btn", 4, Pins("J3"), IOStandard("LVCMOS15")),
  27     ("user_dip_btn", 5, Pins("K3"), IOStandard("LVCMOS15")),
  28     ("user_dip_btn", 6, Pins("J2"), IOStandard("LVCMOS15")),
  29     ("user_dip_btn", 7, Pins("J1"), IOStandard("LVCMOS15")),
  30
  31     ("serial", 0,
  32         Subsignal("tx", Pins("B11"), IOStandard("LVCMOS33")),  # X4 IO0
  33         Subsignal("rx", Pins("B12"), IOStandard("LVCMOS33")),  # X4 IO1
  34     ),
  35
  36     ("eth_clocks", 0,
  37         Subsignal("tx", Pins("C12")),
  38         Subsignal("gtx", Pins("M2")),
  39         Subsignal("rx", Pins("L4")),
  40         IOStandard("LVCMOS33")
  41     ),
  42     ("eth", 0,
  43         Subsignal("rst_n", Pins("L3")),
  44         Subsignal("mdio", Pins("L2")),
  45         Subsignal("mdc", Pins("V4")),
  46         Subsignal("dv", Pins("M1")),
  47         Subsignal("rx_er", Pins("M4")),
  48         Subsignal("rx_data", Pins("M5 N1 N6 P6 T2 R2 P5 P3")),
  49         Subsignal("tx_en", Pins("V3")),
  50         Subsignal("tx_data", Pins("V1 U1 R3 P1 N5 N3 N4 N2")),
  51         Subsignal("col", Pins("R1")),
  52         Subsignal("crs", Pins("P4")),
  53         IOStandard("LVCMOS33")
  54     ),
  55
  56     ("eth_clocks", 1,
  57         Subsignal("tx", Pins("M21")),
  58         Subsignal("gtx", Pins("M19")),
  59         Subsignal("rx", Pins("N19")),
  60         IOStandard("LVCMOS33")
  61     ),
  62     ("eth", 1,
  63         Subsignal("rst_n", Pins("R21")),
  64         Subsignal("mdio", Pins("U16")),
  65         Subsignal("mdc", Pins("Y18")),
  66         Subsignal("dv", Pins("U15")),
  67         Subsignal("rx_er", Pins("V20")),
  68         Subsignal("rx_data", Pins("AB17 AA17 R19 V21 T17 R18 W21 Y21")),
  69         Subsignal("tx_en", Pins("V22")),
  70         Subsignal("tx_data", Pins("W22 R16 P17 Y22 T21 U22 P20 U20")),
  71         Subsignal("col", Pins("N18")),
  72         Subsignal("crs", Pins("P19")),
  73         IOStandard("LVCMOS33")
  74     ),
  75 ]
  76
  77
  78 class Platform(LatticePlatform):
  79     default_clk_name = "clk100"
  80     default_clk_period = 10
  81
  82     def __init__(self):
  83         LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io)
  84
  85     def do_finalize(self, fragment):
  86         LatticePlatform.do_finalize(self, fragment)
  87         try:
  88             self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0)
  89         except ConstraintError:
  90             pass
  91         try:
  92             self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0)
  93         except ConstraintError:
  94             pass
  95     def create_programmer(self):
  96         return LatticeProgrammer()