litex/boards/platforms/versa_ecp5.py

   1 # This file is Copyright (c) 2017 Serge 'q3k' Bazanski <serge@bazanski.pl>
   2 # License: BSD
   3
   4 from litex.build.generic_platform import *
   5 from litex.build.lattice import LatticePlatform
   6 from litex.build.lattice.programmer import LatticeProgrammer
   7
   8 # IOs ----------------------------------------------------------------------------------------------
   9
  10 _io = [
  11     ("clk100", 0, Pins("P3"), IOStandard("LVDS")),
  12     ("rst_n", 0, Pins("T1"), IOStandard("LVCMOS33")),
  13
  14     ("user_led", 0, Pins("E16"), IOStandard("LVCMOS25")),
  15     ("user_led", 1, Pins("D17"), IOStandard("LVCMOS25")),
  16     ("user_led", 2, Pins("D18"), IOStandard("LVCMOS25")),
  17     ("user_led", 3, Pins("E18"), IOStandard("LVCMOS25")),
  18     ("user_led", 4, Pins("F17"), IOStandard("LVCMOS25")),
  19     ("user_led", 5, Pins("F18"), IOStandard("LVCMOS25")),
  20     ("user_led", 6, Pins("E17"), IOStandard("LVCMOS25")),
  21     ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
  22
  23     ("user_dip_btn", 0, Pins("H2"), IOStandard("LVCMOS15")),
  24     ("user_dip_btn", 1, Pins("K3"), IOStandard("LVCMOS15")),
  25     ("user_dip_btn", 2, Pins("G3"), IOStandard("LVCMOS15")),
  26     ("user_dip_btn", 3, Pins("F2"), IOStandard("LVCMOS15")),
  27     ("user_dip_btn", 4, Pins("J18"), IOStandard("LVCMOS25")),
  28     ("user_dip_btn", 5, Pins("K18"), IOStandard("LVCMOS25")),
  29     ("user_dip_btn", 6, Pins("K19"), IOStandard("LVCMOS25")),
  30     ("user_dip_btn", 7, Pins("K20"), IOStandard("LVCMOS25")),
  31
  32     ("serial", 0,
  33         Subsignal("rx", Pins("C11"), IOStandard("LVCMOS33")),
  34         Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")),
  35     ),
  36
  37     ("ddram", 0,
  38         Subsignal("a", Pins(
  39             "P2 C4 E5 F5 B3 F4 B5 E4",
  40             "C5 E3 D5 B4 C3"),
  41             IOStandard("SSTL135_I")),
  42         Subsignal("ba", Pins("P5 N3 M3"), IOStandard("SSTL135_I")),
  43         Subsignal("ras_n", Pins("P1"), IOStandard("SSTL135_I")),
  44         Subsignal("cas_n", Pins("L1"), IOStandard("SSTL135_I")),
  45         Subsignal("we_n", Pins("M1"), IOStandard("SSTL135_I")),
  46         Subsignal("cs_n", Pins("K1"), IOStandard("SSTL135_I")),
  47         Subsignal("dm", Pins("J4 H5"), IOStandard("SSTL135_I")),
  48         Subsignal("dq", Pins(
  49             "L5 F1 K4 G1 L4 H1 G2 J3",
  50             "D1 C1 E2 C2 F3 A2 E1 B1"),
  51             IOStandard("SSTL135_I"),
  52             Misc("TERMINATION=75")),
  53         Subsignal("dqs_p", Pins("K2 H4"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF"), Misc("DIFFRESISTOR=100")),
  54         Subsignal("clk_p", Pins("M4"), IOStandard("SSTL135D_I")),
  55         Subsignal("cke", Pins("N2"), IOStandard("SSTL135_I")),
  56         Subsignal("odt", Pins("L2"), IOStandard("SSTL135_I")),
  57         Subsignal("reset_n", Pins("N4"), IOStandard("SSTL135_I")),
  58         Misc("SLEWRATE=FAST"),
  59     ),
  60
  61     ("eth_clocks", 0,
  62         Subsignal("tx", Pins("P19")),
  63         Subsignal("rx", Pins("L20")),
  64         IOStandard("LVCMOS25")
  65     ),
  66     ("eth", 0,
  67         Subsignal("rst_n", Pins("U17")),
  68         Subsignal("mdio", Pins("U18")),
  69         Subsignal("mdc", Pins("T18")),
  70         Subsignal("rx_ctl", Pins("U19")),
  71         Subsignal("rx_data", Pins("T20 U20 T19 R18")),
  72         Subsignal("tx_ctl", Pins("R20")),
  73         Subsignal("tx_data", Pins("N19 N20 P18 P20")),
  74         IOStandard("LVCMOS25")
  75     ),
  76
  77     ("eth_clocks", 1,
  78         Subsignal("tx", Pins("C20")),
  79         Subsignal("rx", Pins("J19")),
  80         IOStandard("LVCMOS25")
  81     ),
  82     ("eth", 1,
  83         Subsignal("rst_n", Pins("F20")),
  84         Subsignal("mdio", Pins("H20")),
  85         Subsignal("mdc", Pins("G19")),
  86         Subsignal("rx_ctl", Pins("F19")),
  87         Subsignal("rx_data", Pins("G18 G16 H18 H17")),
  88         Subsignal("tx_ctl", Pins("E19")),
  89         Subsignal("tx_data", Pins("J17 J16 D19 D20")),
  90         IOStandard("LVCMOS25")
  91     ),
  92
  93     ("ext_clk", 0,
  94         Subsignal("p", Pins("A4")),
  95         Subsignal("n", Pins("A5")),
  96         IOStandard("LVDS")
  97     ),
  98
  99     ("pcie_x1", 0,
 100         Subsignal("clk_p", Pins("Y11")),
 101         Subsignal("clk_n", Pins("Y12")),
 102         Subsignal("rx_p", Pins("Y5")),
 103         Subsignal("rx_n", Pins("Y6")),
 104         Subsignal("tx_p", Pins("W4")),
 105         Subsignal("tx_n", Pins("W5")),
 106         Subsignal("perst", Pins("A6"), IOStandard("LVCMOS33")),
 107     ),
 108 ]
 109
 110
 111 _ecp5_soc_hat_io = [
 112     ("sdram_clock", 0, Pins("E14"), IOStandard("LVCMOS33")),
 113     ("sdram", 0,
 114          Subsignal("a", Pins(
 115             "C6 E15 A16 B16 D15 C15 B15 E12",
 116             "D12 B10 C7 A9 C10")),
 117          Subsignal("dq", Pins(
 118             "B19 B12 B9 E6 D6 E7 D7 B11",
 119             "C14 A14 E13 D13 C13 B13 A13 A12")),
 120          Subsignal("we_n", Pins("E9")),
 121          Subsignal("ras_n", Pins("B8")),
 122          Subsignal("cas_n", Pins("D9")),
 123          Subsignal("cs_n", Pins("C8")),
 124          Subsignal("cke", Pins("D11")),
 125          Subsignal("ba", Pins("D8 E8")),
 126          Subsignal("dm", Pins("B6 D14")),
 127          IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST")
 128     ),
 129 ]
 130
 131 # Connectors ---------------------------------------------------------------------------------------
 132
 133 _connectors = [
 134    ("X3",
 135         "None",  # (no pin 0)
 136         "None",  #  1 GND
 137         "None",  #  2 N/C
 138         "None",  #  3 +2V5
 139         "B19",   #  4 EXPCON_IO29
 140         "B12",   #  5 EXPCON_IO30
 141         "B9",    #  6 EXPCON_IO31
 142         "E6",    #  7 EXPCON_IO32
 143         "D6",    #  8 EXPCON_IO33
 144         "E7",    #  9 EXPCON_IO34
 145         "D7",    # 10 EXPCON_IO35
 146         "B11",   # 11 EXPCON_IO36
 147         "B6",    # 12 EXPCON_IO37
 148         "E9",    # 13 EXPCON_IO38
 149         "D9",    # 14 EXPCON_IO39
 150         "B8",    # 15 EXPCON_IO40
 151         "C8",    # 16 EXPCON_IO41
 152         "D8",    # 17 EXPCON_IO42
 153         "E8",    # 18 EXPCON_IO43
 154         "C7",    # 19 EXPCON_IO44
 155         "C6",    # 20 EXPCON_IO45
 156         "None",  # 21 +5V
 157         "None",  # 22 GND
 158         "None",  # 23 +2V5
 159         "None",  # 24 GND
 160         "None",  # 25 +3V3
 161         "None",  # 26 GND
 162         "None",  # 27 +3V3
 163         "None",  # 28 GND
 164         "None",  # 29 EXPCON_OSC
 165         "None",  # 30 GND
 166         "None",  # 31 EXPCON_CLKIN
 167         "None",  # 32 GND
 168         "None",  # 33 EXPCON_CLKOUT
 169         "None",  # 34 GND
 170         "None",  # 35 +3V3
 171         "None",  # 36 GND
 172         "None",  # 37 +3V3
 173         "None",  # 38 GND
 174         "None",  # 39 +3V3
 175         "None",  # 40 GND
 176     ),
 177 ]
 178
 179 # Platform -----------------------------------------------------------------------------------------
 180
 181 class Platform(LatticePlatform):
 182     default_clk_name = "clk100"
 183     default_clk_period = 10
 184
 185     def __init__(self, **kwargs):
 186         LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs)
 187
 188     def do_finalize(self, fragment):
 189         try:
 190             self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6)
 191         except ConstraintError:
 192             pass
 193         try:
 194             self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 1e9/125e6)
 195         except ConstraintError:
 196             pass
 197
 198     def create_programmer(self, with_ispclock=True):
 199         _xcf_ispclock = """
 200         <Device>
 201             <SelectedProg value="FALSE"/>
 202             <Pos>2</Pos>
 203             <Vendor>Lattice</Vendor>
 204             <Family>ispCLOCK</Family>
 205             <Name>ispPAC-CLK5406D</Name>
 206             <IDCode>0x00191043</IDCode>
 207             <Operation>Erase,Program,Verify</Operation>
 208             <Bypass>
 209                 <InstrLen>8</InstrLen>
 210                 <InstrVal>11111111</InstrVal>
 211                 <BScanLen>1</BScanLen>
 212                 <BScanVal>0</BScanVal>
 213             </Bypass>
 214         </Device>
 215 """
 216
 217         _xcf_template = """
 218 <?xml version='1.0' encoding='utf-8' ?>
 219 <!DOCTYPE        ispXCF    SYSTEM    "IspXCF.dtd" >
 220 <ispXCF version="3.4.1">
 221     <Comment></Comment>
 222     <Chain>
 223         <Comm>JTAG</Comm>
 224         <Device>
 225             <SelectedProg value="TRUE"/>
 226             <Pos>1</Pos>
 227             <Vendor>Lattice</Vendor>
 228             <Family>ECP5UM5G</Family>
 229             <Name>LFE5UM5G-45F</Name>
 230             <IDCode>0x81112043</IDCode>
 231             <File>{{bitstream_file}}</File>
 232             <Operation>Fast Program</Operation>
 233         </Device>{ispclock}
 234     </Chain>
 235     <ProjectOptions>
 236         <Program>SEQUENTIAL</Program>
 237         <Process>ENTIRED CHAIN</Process>
 238         <OperationOverride>No Override</OperationOverride>
 239         <StartTAP>TLR</StartTAP>
 240         <EndTAP>TLR</EndTAP>
 241         <VerifyUsercode value="FALSE"/>
 242     </ProjectOptions>
 243     <CableOptions>
 244         <CableName>USB2</CableName>
 245         <PortAdd>FTUSB-0</PortAdd>
 246         <USBID>LATTICE ECP5_5G VERSA BOARD A Location 0000 Serial Lattice ECP5_5G VERSA Board A</USBID>
 247     </CableOptions>
 248 </ispXCF>
 249 """.format(ispclock=_xcf_ispclock if with_ispclock else "")
 250
 251         return LatticeProgrammer(_xcf_template)