litex/boards/platforms/versa_ecp5.py

   1 # This file is Copyright (c) 2017 Sergiusz Bazanski <q3k@q3k.org>
   2 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   3 # License: BSD
   4
   5 from litex.build.generic_platform import *
   6 from litex.build.lattice import LatticePlatform
   7 from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
   8
   9 # IOs ----------------------------------------------------------------------------------------------
  10
  11 _io = [
  12     ("clk100", 0, Pins("P3"), IOStandard("LVDS")),
  13     ("rst_n",  0, Pins("T1"), IOStandard("LVCMOS33")),
  14
  15     ("user_led", 0, Pins("E16"), IOStandard("LVCMOS25")),
  16     ("user_led", 1, Pins("D17"), IOStandard("LVCMOS25")),
  17     ("user_led", 2, Pins("D18"), IOStandard("LVCMOS25")),
  18     ("user_led", 3, Pins("E18"), IOStandard("LVCMOS25")),
  19     ("user_led", 4, Pins("F17"), IOStandard("LVCMOS25")),
  20     ("user_led", 5, Pins("F18"), IOStandard("LVCMOS25")),
  21     ("user_led", 6, Pins("E17"), IOStandard("LVCMOS25")),
  22     ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
  23
  24     ("user_dip_btn", 0, Pins("H2"),  IOStandard("LVCMOS15")),
  25     ("user_dip_btn", 1, Pins("K3"),  IOStandard("LVCMOS15")),
  26     ("user_dip_btn", 2, Pins("G3"),  IOStandard("LVCMOS15")),
  27     ("user_dip_btn", 3, Pins("F2"),  IOStandard("LVCMOS15")),
  28     ("user_dip_btn", 4, Pins("J18"), IOStandard("LVCMOS25")),
  29     ("user_dip_btn", 5, Pins("K18"), IOStandard("LVCMOS25")),
  30     ("user_dip_btn", 6, Pins("K19"), IOStandard("LVCMOS25")),
  31     ("user_dip_btn", 7, Pins("K20"), IOStandard("LVCMOS25")),
  32
  33     ("serial", 0,
  34         Subsignal("rx", Pins("C11"), IOStandard("LVCMOS33")),
  35         Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")),
  36     ),
  37
  38     ("spiflash", 0, # clock needs to be accessed through USRMCLK
  39         Subsignal("cs_n", Pins("R2")),
  40         Subsignal("mosi", Pins("W2")),
  41         Subsignal("miso", Pins("V2")),
  42         Subsignal("wp",   Pins("Y2")),
  43         Subsignal("hold", Pins("W1")),
  44         IOStandard("LVCMOS33"),
  45     ),
  46
  47     ("spiflash4x", 0, # clock needs to be accessed through USRMCLK
  48         Subsignal("cs_n", Pins("R2")),
  49         Subsignal("dq",   Pins("W2 V2 Y2 W1")),
  50         IOStandard("LVCMOS33")
  51     ),
  52
  53     ("ddram", 0,
  54         Subsignal("a", Pins(
  55             "P2 C4 E5 F5 B3 F4 B5 E4",
  56             "C5 E3 D5 B4 C3"),
  57             IOStandard("SSTL135_I")),
  58         Subsignal("ba",    Pins("P5 N3 M3"), IOStandard("SSTL135_I")),
  59         Subsignal("ras_n", Pins("P1"), IOStandard("SSTL135_I")),
  60         Subsignal("cas_n", Pins("L1"), IOStandard("SSTL135_I")),
  61         Subsignal("we_n",  Pins("M1"), IOStandard("SSTL135_I")),
  62         Subsignal("cs_n",  Pins("K1"), IOStandard("SSTL135_I")),
  63         Subsignal("dm", Pins("J4 H5"), IOStandard("SSTL135_I")),
  64         Subsignal("dq", Pins(
  65             "L5 F1 K4 G1 L4 H1 G2 J3",
  66             "D1 C1 E2 C2 F3 A2 E1 B1"),
  67             IOStandard("SSTL135_I"),
  68             Misc("TERMINATION=75")),
  69         Subsignal("dqs_p", Pins("K2 H4"), IOStandard("SSTL135D_I"),
  70             Misc("TERMINATION=OFF"),
  71             Misc("DIFFRESISTOR=100")),
  72         Subsignal("clk_p", Pins("M4"), IOStandard("SSTL135D_I")),
  73         Subsignal("cke",   Pins("N2"), IOStandard("SSTL135_I")),
  74         Subsignal("odt",   Pins("L2"), IOStandard("SSTL135_I")),
  75         Subsignal("reset_n", Pins("N4"), IOStandard("SSTL135_I")),
  76         Misc("SLEWRATE=FAST"),
  77     ),
  78
  79     ("eth_clocks", 0,
  80         Subsignal("tx", Pins("P19")),
  81         Subsignal("rx", Pins("L20")),
  82         IOStandard("LVCMOS25")
  83     ),
  84     ("eth", 0,
  85         Subsignal("rst_n",   Pins("U17")),
  86         Subsignal("mdio",    Pins("U18")),
  87         Subsignal("mdc",     Pins("T18")),
  88         Subsignal("rx_ctl",  Pins("U19")),
  89         Subsignal("rx_data", Pins("T20 U20 T19 R18")),
  90         Subsignal("tx_ctl",  Pins("R20")),
  91         Subsignal("tx_data", Pins("N19 N20 P18 P20")),
  92         IOStandard("LVCMOS25")
  93     ),
  94
  95     ("eth_clocks", 1,
  96         Subsignal("tx", Pins("C20")),
  97         Subsignal("rx", Pins("J19")),
  98         IOStandard("LVCMOS25")
  99     ),
 100     ("eth", 1,
 101         Subsignal("rst_n",   Pins("F20")),
 102         Subsignal("mdio",    Pins("H20")),
 103         Subsignal("mdc",     Pins("G19")),
 104         Subsignal("rx_ctl",  Pins("F19")),
 105         Subsignal("rx_data", Pins("G18 G16 H18 H17")),
 106         Subsignal("tx_ctl",  Pins("E19")),
 107         Subsignal("tx_data", Pins("J17 J16 D19 D20")),
 108         IOStandard("LVCMOS25")
 109     ),
 110
 111     ("ext_clk", 0,
 112         Subsignal("p", Pins("A4")),
 113         Subsignal("n", Pins("A5")),
 114         IOStandard("LVDS")
 115     ),
 116
 117     ("pcie_x1", 0,
 118         Subsignal("clk_p", Pins("Y11")),
 119         Subsignal("clk_n", Pins("Y12")),
 120         Subsignal("rx_p",  Pins("Y5")),
 121         Subsignal("rx_n",  Pins("Y6")),
 122         Subsignal("tx_p",  Pins("W4")),
 123         Subsignal("tx_n",  Pins("W5")),
 124         Subsignal("perst", Pins("A6"), IOStandard("LVCMOS33")),
 125     ),
 126
 127     ("refclk_en",    0, Pins("C12"), IOStandard("LVCMOS33")),
 128     ("refclk_rst_n", 0, Pins("R1"),  IOStandard("LVCMOS33")),
 129     ("refclk", 0,
 130         Subsignal("p", Pins("Y11")),
 131         Subsignal("n", Pins("Y12")),
 132     ),
 133     ("refclk", 1,
 134         Subsignal("p", Pins("Y19")),
 135         Subsignal("n", Pins("W20")),
 136     ),
 137
 138     ("sma_tx", 0,
 139         Subsignal("p", Pins("W8")),
 140         Subsignal("n", Pins("W9")),
 141     ),
 142     ("sma_rx", 0,
 143         Subsignal("p", Pins("Y7")),
 144         Subsignal("n", Pins("Y8")),
 145     ),
 146 ]
 147
 148
 149 _ecp5_soc_hat_io = [
 150     ("sdram_clock", 0, Pins("E14"), IOStandard("LVCMOS33")),
 151     ("sdram", 0,
 152          Subsignal("a", Pins(
 153             "C6  E15 A16 B16 D15 C15 B15 E12",
 154             "D12 B10  C7  A9 C10")),
 155          Subsignal("dq", Pins(
 156             "B19 B12  B9  E6  D6  E7  D7 B11",
 157             "C14 A14 E13 D13 C13 B13 A13 A12")),
 158          Subsignal("we_n",  Pins("E9")),
 159          Subsignal("ras_n", Pins("B8")),
 160          Subsignal("cas_n", Pins("D9")),
 161          Subsignal("cs_n",  Pins("C8")),
 162          Subsignal("cke",   Pins("D11")),
 163          Subsignal("ba",    Pins("D8 E8")),
 164          Subsignal("dm",    Pins("B6 D14")),
 165          Misc("SLEWRATE=FAST"),
 166          IOStandard("LVCMOS33"),
 167     ),
 168 ]
 169
 170 # Connectors ---------------------------------------------------------------------------------------
 171
 172 _connectors = [
 173    ("X3",
 174         "None",  # (no pin 0)
 175         "None",  #  1 GND
 176         "None",  #  2 N/C
 177         "None",  #  3 +2V5
 178         "B19",   #  4 EXPCON_IO29
 179         "B12",   #  5 EXPCON_IO30
 180         "B9",    #  6 EXPCON_IO31
 181         "E6",    #  7 EXPCON_IO32
 182         "D6",    #  8 EXPCON_IO33
 183         "E7",    #  9 EXPCON_IO34
 184         "D7",    # 10 EXPCON_IO35
 185         "B11",   # 11 EXPCON_IO36
 186         "B6",    # 12 EXPCON_IO37
 187         "E9",    # 13 EXPCON_IO38
 188         "D9",    # 14 EXPCON_IO39
 189         "B8",    # 15 EXPCON_IO40
 190         "C8",    # 16 EXPCON_IO41
 191         "D8",    # 17 EXPCON_IO42
 192         "E8",    # 18 EXPCON_IO43
 193         "C7",    # 19 EXPCON_IO44
 194         "C6",    # 20 EXPCON_IO45
 195         "None",  # 21 +5V
 196         "None",  # 22 GND
 197         "None",  # 23 +2V5
 198         "None",  # 24 GND
 199         "None",  # 25 +3V3
 200         "None",  # 26 GND
 201         "None",  # 27 +3V3
 202         "None",  # 28 GND
 203         "None",  # 29 EXPCON_OSC
 204         "None",  # 30 GND
 205         "None",  # 31 EXPCON_CLKIN
 206         "None",  # 32 GND
 207         "None",  # 33 EXPCON_CLKOUT
 208         "None",  # 34 GND
 209         "None",  # 35 +3V3
 210         "None",  # 36 GND
 211         "None",  # 37 +3V3
 212         "None",  # 38 GND
 213         "None",  # 39 +3V3
 214         "None",  # 40 GND
 215     ),
 216 ]
 217
 218 # Platform -----------------------------------------------------------------------------------------
 219
 220 class Platform(LatticePlatform):
 221     default_clk_name   = "clk100"
 222     default_clk_period = 1e9/100e6
 223
 224     def __init__(self, device="LFE5UM5G", **kwargs):
 225         assert device in ["LFE5UM5G", "LFE5UM"]
 226         LatticePlatform.__init__(self, device + "-45F-8BG381C", _io, _connectors, **kwargs)
 227
 228     def create_programmer(self):
 229         return OpenOCDJTAGProgrammer("openocd_versa_ecp5.cfg")
 230
 231     def do_finalize(self, fragment):
 232         self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
 233         self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
 234         self.add_period_constraint(self.lookup_request("eth_clocks:rx", 1, loose=True), 1e9/125e6)