Add Versa ECP5-5G Platform.
[litex.git] / litex / boards / platforms / versaecp55g.py
1 # This file is Copyright (c) 2017 Serge 'q3k' Bazanski <serge@bazanski.pl>
2 # License: BSD
3
4 from litex.build.generic_platform import *
5 from litex.build.lattice import LatticePlatform
6 from litex.build.lattice.programmer import LatticeProgrammer
7
8
9 _io = [
10 ("clk100", 0, Pins("P3"), IOStandard("LVDS")),
11 ("rst_n", 0, Pins("T1"), IOStandard("LVCMOS33")),
12
13 ("user_led", 0, Pins("E16"), IOStandard("LVCMOS25")),
14 ("user_led", 1, Pins("D17"), IOStandard("LVCMOS25")),
15 ("user_led", 2, Pins("D18"), IOStandard("LVCMOS25")),
16 ("user_led", 3, Pins("E18"), IOStandard("LVCMOS25")),
17 ("user_led", 4, Pins("F17"), IOStandard("LVCMOS25")),
18 ("user_led", 5, Pins("F18"), IOStandard("LVCMOS25")),
19 ("user_led", 6, Pins("E17"), IOStandard("LVCMOS25")),
20 ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
21
22 ("user_dip_btn", 0, Pins("H2"), IOStandard("LVCMOS15")),
23 ("user_dip_btn", 1, Pins("K3"), IOStandard("LVCMOS15")),
24 ("user_dip_btn", 2, Pins("G3"), IOStandard("LVCMOS15")),
25 ("user_dip_btn", 3, Pins("F2"), IOStandard("LVCMOS15")),
26 ("user_dip_btn", 4, Pins("J18"), IOStandard("LVCMOS25")),
27 ("user_dip_btn", 5, Pins("K18"), IOStandard("LVCMOS25")),
28 ("user_dip_btn", 6, Pins("K19"), IOStandard("LVCMOS25")),
29 ("user_dip_btn", 7, Pins("K20"), IOStandard("LVCMOS25")),
30
31 ("serial", 0,
32 Subsignal("tx", Pins("A12"), IOStandard("LVCMOS33")), # X4 IO0
33 Subsignal("rx", Pins("A13"), IOStandard("LVCMOS33")), # X4 IO1
34 ),
35
36 ("eth_clocks", 0,
37 Subsignal("tx", Pins("P19")),
38 Subsignal("rx", Pins("L20")),
39 IOStandard("LVCMOS25")
40 ),
41 ("eth", 0,
42 Subsignal("rst_n", Pins("U17")),
43 Subsignal("mdio", Pins("U18")),
44 Subsignal("mdc", Pins("T18")),
45 Subsignal("rx_ctl", Pins("U19")),
46 Subsignal("rx_data", Pins("T20 U20 T19 R18")),
47 Subsignal("tx_ctl", Pins("R20")),
48 Subsignal("tx_data", Pins("N19 N20 P18 P20")),
49 IOStandard("LVCMOS25")
50 ),
51
52 ("eth_clocks", 1,
53 Subsignal("tx", Pins("C20")),
54 Subsignal("rx", Pins("J19")),
55 IOStandard("LVCMOS25")
56 ),
57 ("eth", 1,
58 Subsignal("rst_n", Pins("F20")),
59 Subsignal("mdio", Pins("H20")),
60 Subsignal("mdc", Pins("G19")),
61 Subsignal("rx_ctl", Pins("F19")),
62 Subsignal("rx_data", Pins("G18 G16 H18 H17")),
63 Subsignal("tx_ctl", Pins("E19")),
64 Subsignal("tx_data", Pins("J17 J16 D19 D20")),
65 IOStandard("LVCMOS25")
66 ),
67 ]
68
69
70 class Platform(LatticePlatform):
71 default_clk_name = "clk100"
72 default_clk_period = 10
73
74 def __init__(self, **kwargs):
75 LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, **kwargs)
76
77 def do_finalize(self, fragment):
78 LatticePlatform.do_finalize(self, fragment)
79 try:
80 self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0)
81 except ConstraintError:
82 pass
83 try:
84 self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0)
85 except ConstraintError:
86 pass
87
88 def create_programmer(self):
89 _xcf_template = """
90 <?xml version='1.0' encoding='utf-8' ?>
91 <!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
92 <ispXCF version="3.4.1">
93 <Comment></Comment>
94 <Chain>
95 <Comm>JTAG</Comm>
96 <Device>
97 <SelectedProg value="TRUE"/>
98 <Pos>1</Pos>
99 <Vendor>Lattice</Vendor>
100 <Family>ECP5UM5G</Family>
101 <Name>LFE5UM5G-45F</Name>
102 <IDCode>0x81112043</IDCode>
103 <File>{bitstream_file}</File>
104 <Operation>Fast Program</Operation>
105 </Device>
106 <Device>
107 <SelectedProg value="FALSE"/>
108 <Pos>2</Pos>
109 <Vendor>Lattice</Vendor>
110 <Family>ispCLOCK</Family>
111 <Name>ispPAC-CLK5406D</Name>
112 <IDCode>0x00191043</IDCode>
113 <Operation>Erase,Program,Verify</Operation>
114 <Bypass>
115 <InstrLen>8</InstrLen>
116 <InstrVal>11111111</InstrVal>
117 <BScanLen>1</BScanLen>
118 <BScanVal>0</BScanVal>
119 </Bypass>
120 </Device>
121 </Chain>
122 <ProjectOptions>
123 <Program>SEQUENTIAL</Program>
124 <Process>ENTIRED CHAIN</Process>
125 <OperationOverride>No Override</OperationOverride>
126 <StartTAP>TLR</StartTAP>
127 <EndTAP>TLR</EndTAP>
128 <VerifyUsercode value="FALSE"/>
129 </ProjectOptions>
130 <CableOptions>
131 <CableName>USB2</CableName>
132 <PortAdd>FTUSB-0</PortAdd>
133 <USBID>LATTICE ECP5_5G VERSA BOARD A Location 0000 Serial Lattice ECP5_5G VERSA Board A</USBID>
134 </CableOptions>
135 </ispXCF>
136 """
137
138 return LatticeProgrammer(_xcf_template)