litex/boards/targets/arty.py

   1 #!/usr/bin/env python3
   2 import argparse
   3 import os
   4
   5 from litex.gen import *
   6 from litex.gen.genlib.resetsync import AsyncResetSynchronizer
   7
   8 from litex.boards.platforms import arty
   9
  10 from litex.soc.integration.soc_core import *
  11 from litex.soc.integration.builder import *
  12
  13 from liteeth.phy.mii import LiteEthPHYMII
  14 from liteeth.core.mac import LiteEthMAC
  15
  16 class _CRG(Module):
  17     def __init__(self, platform):
  18         self.clock_domains.cd_sys = ClockDomain()
  19         self.clock_domains.cd_eth = ClockDomain(reset_less=True)
  20
  21         clk100 = platform.request("clk100")
  22         rst = platform.request("cpu_reset")
  23
  24         pll_locked = Signal()
  25         pll_fb = Signal()
  26         pll_sys = Signal()
  27         pll_eth = Signal()
  28         self.specials += [
  29             Instance("PLLE2_BASE",
  30                      p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
  31
  32                      # VCO @ 800 MHz
  33                      p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0,
  34                      p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
  35                      i_CLKIN1=clk100, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
  36
  37                      # 100 MHz
  38                      p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0,
  39                      o_CLKOUT0=pll_sys,
  40
  41                      # 25 MHz
  42                      p_CLKOUT1_DIVIDE=32, p_CLKOUT1_PHASE=0.0,
  43                      o_CLKOUT1=pll_eth,
  44
  45                      # 200 MHz
  46                      p_CLKOUT2_DIVIDE=4, p_CLKOUT2_PHASE=0.0,
  47                      #o_CLKOUT2=,
  48
  49                      # 200 MHz
  50                      p_CLKOUT3_DIVIDE=4, p_CLKOUT3_PHASE=0.0,
  51                      #o_CLKOUT3=,
  52
  53                      # 200MHz
  54                      p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0,
  55                      #o_CLKOUT4=
  56             ),
  57             Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
  58             Instance("BUFG", i_I=pll_eth, o_O=self.cd_eth.clk),
  59             AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~rst),
  60         ]
  61
  62
  63         self.specials += [
  64             Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
  65                      p_INIT=0, p_SRTYPE="SYNC",
  66                      i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
  67                      i_C0=self.cd_eth.clk, i_C1=~self.cd_eth.clk,
  68                      o_Q=platform.request("eth_ref_clk"))
  69         ]
  70
  71
  72 class BaseSoC(SoCCore):
  73     def __init__(self, **kwargs):
  74         platform = arty.Platform()
  75         SoCCore.__init__(self, platform, clk_freq=100*1000000,
  76                          integrated_rom_size=0x8000,
  77                          integrated_sram_size=0x8000,
  78                          integrated_main_ram_size=0x10000,
  79                          **kwargs)
  80
  81         self.submodules.crg = _CRG(platform)
  82
  83
  84 class MiniSoC(BaseSoC):
  85     csr_map = {
  86         "ethphy": 18,
  87         "ethmac": 19
  88     }
  89     csr_map.update(BaseSoC.csr_map)
  90
  91     interrupt_map = {
  92         "ethmac": 2,
  93     }
  94     interrupt_map.update(BaseSoC.interrupt_map)
  95
  96     mem_map = {
  97         "ethmac": 0x30000000,  # (shadow @0xb0000000)
  98     }
  99     mem_map.update(BaseSoC.mem_map)
 100
 101     def __init__(self, **kwargs):
 102         BaseSoC.__init__(self, **kwargs)
 103
 104         self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"),
 105                                                self.platform.request("eth"))
 106         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
 107         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
 108         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 109
 110
 111 def main():
 112     parser = argparse.ArgumentParser(description="LiteX SoC port to Arty")
 113     builder_args(parser)
 114     soc_core_args(parser)
 115     parser.add_argument("--with-ethernet", action="store_true",
 116                         help="enable Ethernet support")
 117     args = parser.parse_args()
 118
 119     cls = MiniSoC if args.with_ethernet else BaseSoC
 120     soc = cls(**soc_core_argdict(args))
 121     builder = Builder(soc, **builder_argdict(args))
 122     builder.build()
 123
 124
 125 if __name__ == "__main__":
 126     main()