litex/boards/targets/genesys2.py

   1 #!/usr/bin/env python3
   2
   3 import argparse
   4
   5 from migen import *
   6
   7 from litex.boards.platforms import genesys2
   8
   9 from litex.soc.cores.clock import *
  10 from litex.soc.integration.soc_core import mem_decoder
  11 from litex.soc.integration.soc_sdram import *
  12 from litex.soc.integration.builder import *
  13
  14 from litedram.modules import MT41J256M16
  15 from litedram.phy import s7ddrphy
  16
  17 from liteeth.phy.s7rgmii import LiteEthPHYRGMII
  18 from liteeth.core.mac import LiteEthMAC
  19
  20 # CRG ----------------------------------------------------------------------------------------------
  21
  22 class _CRG(Module):
  23     def __init__(self, platform, sys_clk_freq):
  24         self.clock_domains.cd_sys = ClockDomain()
  25         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
  26         self.clock_domains.cd_clk200 = ClockDomain()
  27
  28         self.submodules.pll = pll = S7MMCM(speedgrade=-2)
  29         self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
  30         pll.register_clkin(platform.request("clk200"), 200e6)
  31         pll.create_clkout(self.cd_sys, sys_clk_freq)
  32         pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
  33         pll.create_clkout(self.cd_clk200, 200e6)
  34
  35         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
  36
  37 # BaseSoC ------------------------------------------------------------------------------------------
  38
  39 class BaseSoC(SoCSDRAM):
  40     csr_map = {
  41         "ddrphy":    16,
  42     }
  43     csr_map.update(SoCSDRAM.csr_map)
  44     def __init__(self, **kwargs):
  45         platform = genesys2.Platform()
  46         sys_clk_freq = int(125e6)
  47         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
  48                          integrated_rom_size=0x8000,
  49                          integrated_sram_size=0x8000,
  50                           **kwargs)
  51
  52         self.submodules.crg = _CRG(platform, sys_clk_freq)
  53
  54         # sdram
  55         self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
  56         sdram_module = MT41J256M16(self.clk_freq, "1:4")
  57         self.register_sdram(self.ddrphy,
  58                             sdram_module.geom_settings,
  59                             sdram_module.timing_settings)
  60
  61 # EthernetSoC ------------------------------------------------------------------------------------------
  62
  63 class EthernetSoC(BaseSoC):
  64     csr_map = {
  65         "ethphy": 18,
  66         "ethmac": 19
  67     }
  68     csr_map.update(BaseSoC.csr_map)
  69
  70     interrupt_map = {
  71         "ethmac": 3,
  72     }
  73     interrupt_map.update(BaseSoC.interrupt_map)
  74
  75     mem_map = {
  76         "ethmac": 0x30000000,  # (shadow @0xb0000000)
  77     }
  78     mem_map.update(BaseSoC.mem_map)
  79
  80     def __init__(self, **kwargs):
  81         BaseSoC.__init__(self, **kwargs)
  82
  83         self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
  84                                                  self.platform.request("eth"))
  85         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
  86             interface="wishbone", endianness=self.cpu.endianness)
  87         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
  88         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
  89
  90         self.crg.cd_sys.clk.attr.add("keep")
  91         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
  92         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
  93         self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
  94         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
  95         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
  96         self.platform.add_false_path_constraints(
  97             self.crg.cd_sys.clk,
  98             self.ethphy.crg.cd_eth_rx.clk,
  99             self.ethphy.crg.cd_eth_tx.clk)
 100
 101 # Build --------------------------------------------------------------------------------------------
 102
 103 def main():
 104     parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2")
 105     builder_args(parser)
 106     soc_sdram_args(parser)
 107     parser.add_argument("--with-ethernet", action="store_true",
 108                         help="enable Ethernet support")
 109     args = parser.parse_args()
 110
 111     cls = EthernetSoC if args.with_ethernet else BaseSoC
 112     soc = cls(**soc_sdram_argdict(args))
 113     builder = Builder(soc, **builder_argdict(args))
 114     builder.build()
 115
 116
 117 if __name__ == "__main__":
 118     main()