litex/boards/targets/genesys2.py

   1 #!/usr/bin/env python3
   2
   3 import argparse
   4
   5 from migen import *
   6
   7 from litex.boards.platforms import genesys2
   8
   9 from litex.soc.cores.clock import *
  10 from litex.soc.integration.soc_core import mem_decoder
  11 from litex.soc.integration.soc_sdram import *
  12 from litex.soc.integration.builder import *
  13
  14 from litedram.modules import MT41J256M16
  15 from litedram.phy import s7ddrphy
  16
  17 from liteeth.phy.s7rgmii import LiteEthPHYRGMII
  18 from liteeth.core.mac import LiteEthMAC
  19
  20 # CRG ----------------------------------------------------------------------------------------------
  21
  22 class _CRG(Module):
  23     def __init__(self, platform, sys_clk_freq):
  24         self.clock_domains.cd_sys = ClockDomain()
  25         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
  26         self.clock_domains.cd_clk200 = ClockDomain()
  27
  28         # # #
  29
  30         self.cd_sys.clk.attr.add("keep")
  31         self.cd_sys4x.clk.attr.add("keep")
  32
  33         self.submodules.pll = pll = S7MMCM(speedgrade=-2)
  34         self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
  35         pll.register_clkin(platform.request("clk200"), 200e6)
  36         pll.create_clkout(self.cd_sys, sys_clk_freq)
  37         pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
  38         pll.create_clkout(self.cd_clk200, 200e6)
  39
  40         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
  41
  42 # BaseSoC ------------------------------------------------------------------------------------------
  43
  44 class BaseSoC(SoCSDRAM):
  45     csr_map = {
  46         "ddrphy":    16,
  47     }
  48     csr_map.update(SoCSDRAM.csr_map)
  49     def __init__(self, sys_clk_freq=int(125e6), **kwargs):
  50         platform = genesys2.Platform()
  51         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
  52                          integrated_rom_size=0x8000,
  53                          integrated_sram_size=0x8000,
  54                           **kwargs)
  55
  56         self.submodules.crg = _CRG(platform, sys_clk_freq)
  57
  58         # sdram
  59         self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
  60         sdram_module = MT41J256M16(self.clk_freq, "1:4")
  61         self.register_sdram(self.ddrphy,
  62                             sdram_module.geom_settings,
  63                             sdram_module.timing_settings)
  64
  65 # EthernetSoC ------------------------------------------------------------------------------------------
  66
  67 class EthernetSoC(BaseSoC):
  68     csr_map = {
  69         "ethphy": 18,
  70         "ethmac": 19
  71     }
  72     csr_map.update(BaseSoC.csr_map)
  73
  74     interrupt_map = {
  75         "ethmac": 3,
  76     }
  77     interrupt_map.update(BaseSoC.interrupt_map)
  78
  79     mem_map = {
  80         "ethmac": 0x30000000,  # (shadow @0xb0000000)
  81     }
  82     mem_map.update(BaseSoC.mem_map)
  83
  84     def __init__(self, **kwargs):
  85         BaseSoC.__init__(self, **kwargs)
  86
  87         self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
  88                                                  self.platform.request("eth"))
  89         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
  90             interface="wishbone", endianness=self.cpu.endianness)
  91         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
  92         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
  93
  94         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
  95         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
  96         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
  97         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
  98         self.platform.add_false_path_constraints(
  99             self.crg.cd_sys.clk,
 100             self.ethphy.crg.cd_eth_rx.clk,
 101             self.ethphy.crg.cd_eth_tx.clk)
 102
 103 # Build --------------------------------------------------------------------------------------------
 104
 105 def main():
 106     parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2")
 107     builder_args(parser)
 108     soc_sdram_args(parser)
 109     parser.add_argument("--with-ethernet", action="store_true",
 110                         help="enable Ethernet support")
 111     args = parser.parse_args()
 112
 113     cls = EthernetSoC if args.with_ethernet else BaseSoC
 114     soc = cls(**soc_sdram_argdict(args))
 115     builder = Builder(soc, **builder_argdict(args))
 116     builder.build()
 117
 118
 119 if __name__ == "__main__":
 120     main()