litex/boards/targets/minispartan6.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
   4 # This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   5 # This file is Copyright (c) 2014 Yann Sionneau <ys@m-labs.hk>
   6 # License: BSD
   7
   8 import os
   9 import argparse
  10 from fractions import Fraction
  11
  12 from migen import *
  13 from migen.genlib.resetsync import AsyncResetSynchronizer
  14
  15 from litex.build.io import DDROutput
  16
  17 from litex.boards.platforms import minispartan6
  18
  19 from litex.soc.cores.clock import *
  20 from litex.soc.integration.soc_core import *
  21 from litex.soc.integration.soc_sdram import *
  22 from litex.soc.integration.builder import *
  23
  24 from litedram.modules import AS4C16M16
  25 from litedram.phy import GENSDRPHY
  26
  27 # CRG ----------------------------------------------------------------------------------------------
  28
  29 class _CRG(Module):
  30     def __init__(self, platform, clk_freq):
  31         self.clock_domains.cd_sys    = ClockDomain()
  32         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
  33
  34         # # #
  35
  36         self.submodules.pll = pll = S6PLL(speedgrade=-1)
  37         pll.register_clkin(platform.request("clk32"), 32e6)
  38         pll.create_clkout(self.cd_sys,    clk_freq)
  39         pll.create_clkout(self.cd_sys_ps, clk_freq, phase=90)
  40
  41         # SDRAM clock
  42         self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
  43
  44 # BaseSoC ------------------------------------------------------------------------------------------
  45
  46 class BaseSoC(SoCCore):
  47     def __init__(self, sys_clk_freq=int(80e6), **kwargs):
  48         platform = minispartan6.Platform()
  49
  50         # SoCCore ----------------------------------------------------------------------------------
  51         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
  52
  53         # CRG --------------------------------------------------------------------------------------
  54         self.submodules.crg = _CRG(platform, sys_clk_freq)
  55
  56         # SDR SDRAM --------------------------------------------------------------------------------
  57         if not self.integrated_main_ram_size:
  58             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
  59             self.add_sdram("sdram",
  60                 phy                     = self.sdrphy,
  61                 module                  = AS4C16M16(sys_clk_freq, "1:1"),
  62                 origin                  = self.mem_map["main_ram"],
  63                 size                    = kwargs.get("max_sdram_size", 0x40000000),
  64                 l2_cache_size           = kwargs.get("l2_size", 8192),
  65                 l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
  66                 l2_cache_reverse        = True
  67             )
  68
  69 # Build --------------------------------------------------------------------------------------------
  70
  71 def main():
  72     parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6")
  73     parser.add_argument("--build", action="store_true", help="Build bitstream")
  74     parser.add_argument("--load",  action="store_true", help="Load bitstream")
  75     builder_args(parser)
  76     soc_sdram_args(parser)
  77     args = parser.parse_args()
  78
  79     soc = BaseSoC(**soc_sdram_argdict(args))
  80     builder = Builder(soc, **builder_argdict(args))
  81     builder.build(run=args.build)
  82
  83     if args.load:
  84         prog = soc.platform.create_programmer()
  85         prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
  86
  87 if __name__ == "__main__":
  88     main()