litex/boards/targets/netv2.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # License: BSD
   5
   6 import argparse
   7
   8 from migen import *
   9
  10 from litex.boards.platforms import netv2
  11
  12 from litex.soc.cores.clock import *
  13 from litex.soc.integration.soc_core import *
  14 from litex.soc.integration.soc_sdram import *
  15 from litex.soc.integration.builder import *
  16 from litex.soc.integration.soc import *
  17
  18 from litedram.modules import K4B2G1646F
  19 from litedram.phy import s7ddrphy
  20
  21 from liteeth.phy.rmii import LiteEthPHYRMII
  22
  23 from litespi import LiteSPI
  24 from litespi.phy.generic import LiteSPIPHY
  25
  26 # CRG ----------------------------------------------------------------------------------------------
  27
  28 class _CRG(Module):
  29     def __init__(self, platform, sys_clk_freq):
  30         self.clock_domains.cd_sys       = ClockDomain()
  31         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
  32         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
  33         self.clock_domains.cd_clk200    = ClockDomain()
  34         self.clock_domains.cd_clk100    = ClockDomain()
  35         self.clock_domains.cd_eth       = ClockDomain()
  36
  37         # # #
  38
  39         self.submodules.pll = pll = S7PLL(speedgrade=-1)
  40         pll.register_clkin(platform.request("clk50"), 50e6)
  41         pll.create_clkout(self.cd_sys,       sys_clk_freq)
  42         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
  43         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
  44         pll.create_clkout(self.cd_clk200,    200e6)
  45         pll.create_clkout(self.cd_clk100,    100e6)
  46         pll.create_clkout(self.cd_eth,       50e6)
  47
  48         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
  49
  50 # BaseSoC ------------------------------------------------------------------------------------------
  51
  52 class BaseSoC(SoCCore):
  53     def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_spi_xip=False, **kwargs):
  54         platform = netv2.Platform()
  55
  56         # SoCCore ----------------------------------------------------------------------------------
  57         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
  58
  59         # CRG --------------------------------------------------------------------------------------
  60         self.submodules.crg = _CRG(platform, sys_clk_freq)
  61
  62         # DDR3 SDRAM -------------------------------------------------------------------------------
  63         if not self.integrated_main_ram_size:
  64             self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
  65                 memtype      = "DDR3",
  66                 nphases      = 4,
  67                 sys_clk_freq = sys_clk_freq)
  68             self.add_csr("ddrphy")
  69             self.add_sdram("sdram",
  70                 phy                     = self.ddrphy,
  71                 module                  = K4B2G1646F(sys_clk_freq, "1:4"),
  72                 origin                  = self.mem_map["main_ram"],
  73                 size                    = kwargs.get("max_sdram_size", 0x40000000),
  74                 l2_cache_size           = kwargs.get("l2_size", 8192),
  75                 l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
  76                 l2_cache_reverse        = True
  77             )
  78
  79         # SPI XIP ----------------------------------------------------------------------------------
  80         if with_spi_xip:
  81             spi_xip_size = 1024*1024*8
  82             self.submodules.spiphy = LiteSPIPHY(platform.request("spiflash4x"))
  83             self.submodules.spictl = LiteSPI(phy=self.spiphy, endianness=self.cpu.endianness)
  84             spi_xip_region = SoCRegion(origin=self.mem_map.get("spixip", None), size=spi_xip_size, cached=False)
  85             self.bus.add_slave(name="spixip", slave=self.spictl.bus, region=spi_xip_region)
  86
  87         # Ethernet ---------------------------------------------------------------------------------
  88         if with_ethernet:
  89             self.submodules.ethphy = LiteEthPHYRMII(
  90                 clock_pads = self.platform.request("eth_clocks"),
  91                 pads       = self.platform.request("eth"))
  92             self.add_csr("ethphy")
  93             self.add_ethernet(phy=self.ethphy)
  94
  95 # Build --------------------------------------------------------------------------------------------
  96
  97 def main():
  98     parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2")
  99     builder_args(parser)
 100     soc_sdram_args(parser)
 101     parser.add_argument("--with-ethernet", action="store_true",
 102                         help="enable Ethernet support")
 103     parser.add_argument("--with-spi-xip", action="store_true",
 104                         help="enable SPI XIP support")
 105     args = parser.parse_args()
 106
 107     soc = BaseSoC(with_ethernet=args.with_ethernet, with_spi_xip=args.with_spi_xip, **soc_sdram_argdict(args))
 108     builder = Builder(soc, **builder_argdict(args))
 109     builder.build()
 110
 111
 112 if __name__ == "__main__":
 113     main()