litex/boards/targets/netv2.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # License: BSD
   5
   6 import os
   7 import argparse
   8
   9 from migen import *
  10
  11 from litex.boards.platforms import netv2
  12
  13 from litex.soc.cores.clock import *
  14 from litex.soc.integration.soc_core import *
  15 from litex.soc.integration.soc_sdram import *
  16 from litex.soc.integration.builder import *
  17 from litex.soc.integration.soc import *
  18
  19 from litedram.modules import K4B2G1646F
  20 from litedram.phy import s7ddrphy
  21
  22 from liteeth.phy.rmii import LiteEthPHYRMII
  23
  24 # CRG ----------------------------------------------------------------------------------------------
  25
  26 class _CRG(Module):
  27     def __init__(self, platform, sys_clk_freq):
  28         self.clock_domains.cd_sys       = ClockDomain()
  29         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
  30         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
  31         self.clock_domains.cd_clk200    = ClockDomain()
  32         self.clock_domains.cd_clk100    = ClockDomain()
  33         self.clock_domains.cd_eth       = ClockDomain()
  34
  35         # # #
  36
  37         self.submodules.pll = pll = S7PLL(speedgrade=-1)
  38         pll.register_clkin(platform.request("clk50"), 50e6)
  39         pll.create_clkout(self.cd_sys,       sys_clk_freq)
  40         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
  41         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
  42         pll.create_clkout(self.cd_clk200,    200e6)
  43         pll.create_clkout(self.cd_clk100,    100e6)
  44         pll.create_clkout(self.cd_eth,       50e6)
  45
  46         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
  47
  48 # BaseSoC ------------------------------------------------------------------------------------------
  49
  50 class BaseSoC(SoCCore):
  51     def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_spi_xip=False, **kwargs):
  52         platform = netv2.Platform()
  53
  54         # SoCCore ----------------------------------------------------------------------------------
  55         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
  56
  57         # CRG --------------------------------------------------------------------------------------
  58         self.submodules.crg = _CRG(platform, sys_clk_freq)
  59
  60         # DDR3 SDRAM -------------------------------------------------------------------------------
  61         if not self.integrated_main_ram_size:
  62             self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
  63                 memtype      = "DDR3",
  64                 nphases      = 4,
  65                 sys_clk_freq = sys_clk_freq)
  66             self.add_csr("ddrphy")
  67             self.add_sdram("sdram",
  68                 phy                     = self.ddrphy,
  69                 module                  = K4B2G1646F(sys_clk_freq, "1:4"),
  70                 origin                  = self.mem_map["main_ram"],
  71                 size                    = kwargs.get("max_sdram_size", 0x40000000),
  72                 l2_cache_size           = kwargs.get("l2_size", 8192),
  73                 l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
  74                 l2_cache_reverse        = True
  75             )
  76
  77         # SPI XIP ----------------------------------------------------------------------------------
  78         if with_spi_xip:
  79             from litespi import LiteSPI
  80             from litespi.phy.generic import LiteSPIPHY
  81             spi_xip_size = 1024*1024*8
  82             self.submodules.spiphy = LiteSPIPHY(platform.request("spiflash4x"))
  83             self.submodules.spictl = LiteSPI(phy=self.spiphy, endianness=self.cpu.endianness)
  84             spi_xip_region = SoCRegion(origin=self.mem_map.get("spixip", None), size=spi_xip_size, cached=False)
  85             self.bus.add_slave(name="spixip", slave=self.spictl.bus, region=spi_xip_region)
  86
  87         # Ethernet ---------------------------------------------------------------------------------
  88         if with_ethernet:
  89             self.submodules.ethphy = LiteEthPHYRMII(
  90                 clock_pads = self.platform.request("eth_clocks"),
  91                 pads       = self.platform.request("eth"))
  92             self.add_csr("ethphy")
  93             self.add_ethernet(phy=self.ethphy)
  94
  95 # Build --------------------------------------------------------------------------------------------
  96
  97 def main():
  98     parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2")
  99     parser.add_argument("--build", action="store_true", help="Build bitstream")
 100     parser.add_argument("--load",  action="store_true", help="Load bitstream")
 101     builder_args(parser)
 102     soc_sdram_args(parser)
 103     parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
 104     parser.add_argument("--with-spi-xip",  action="store_true", help="Enable SPI XIP support")
 105     args = parser.parse_args()
 106
 107     soc = BaseSoC(with_ethernet=args.with_ethernet, with_spi_xip=args.with_spi_xip, **soc_sdram_argdict(args))
 108     builder = Builder(soc, **builder_argdict(args))
 109     builder.build(run=args.build)
 110
 111     if args.load:
 112         prog = soc.platform.create_programmer()
 113         prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
 114
 115 if __name__ == "__main__":
 116     main()