3 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
10 from litex
.boards
.platforms
import netv2
12 from litex
.soc
.cores
.clock
import *
13 from litex
.soc
.integration
.soc_sdram
import *
14 from litex
.soc
.integration
.builder
import *
16 from litedram
.modules
import K4B2G1646F
17 from litedram
.phy
import s7ddrphy
19 from liteeth
.phy
.rmii
import LiteEthPHYRMII
20 from liteeth
.mac
import LiteEthMAC
22 # CRG ----------------------------------------------------------------------------------------------
25 def __init__(self
, platform
, sys_clk_freq
):
26 self
.clock_domains
.cd_sys
= ClockDomain()
27 self
.clock_domains
.cd_sys4x
= ClockDomain(reset_less
=True)
28 self
.clock_domains
.cd_sys4x_dqs
= ClockDomain(reset_less
=True)
29 self
.clock_domains
.cd_clk200
= ClockDomain()
30 self
.clock_domains
.cd_clk100
= ClockDomain()
31 self
.clock_domains
.cd_eth
= ClockDomain()
35 self
.submodules
.pll
= pll
= S7PLL(speedgrade
=-1)
36 pll
.register_clkin(platform
.request("clk50"), 50e6
)
37 pll
.create_clkout(self
.cd_sys
, sys_clk_freq
)
38 pll
.create_clkout(self
.cd_sys4x
, 4*sys_clk_freq
)
39 pll
.create_clkout(self
.cd_sys4x_dqs
, 4*sys_clk_freq
, phase
=90)
40 pll
.create_clkout(self
.cd_clk200
, 200e6
)
41 pll
.create_clkout(self
.cd_clk100
, 100e6
)
42 pll
.create_clkout(self
.cd_eth
, 50e6
)
44 self
.submodules
.idelayctrl
= S7IDELAYCTRL(self
.cd_clk200
)
46 # BaseSoC ------------------------------------------------------------------------------------------
48 class BaseSoC(SoCSDRAM
):
49 def __init__(self
, sys_clk_freq
=int(100e6
), **kwargs
):
50 platform
= netv2
.Platform()
52 # SoCSDRAM ---------------------------------------------------------------------------------
53 SoCSDRAM
.__init
__(self
, platform
, clk_freq
=sys_clk_freq
, **kwargs
)
55 # CRG --------------------------------------------------------------------------------------
56 self
.submodules
.crg
= _CRG(platform
, sys_clk_freq
)
58 # DDR3 SDRAM -------------------------------------------------------------------------------
59 if not self
.integrated_main_ram_size
:
60 self
.submodules
.ddrphy
= s7ddrphy
.A7DDRPHY(platform
.request("ddram"),
63 sys_clk_freq
= sys_clk_freq
)
64 self
.add_csr("ddrphy")
65 sdram_module
= K4B2G1646F(sys_clk_freq
, "1:4")
66 self
.register_sdram(self
.ddrphy
,
67 geom_settings
= sdram_module
.geom_settings
,
68 timing_settings
= sdram_module
.timing_settings
)
70 # EthernetSoC --------------------------------------------------------------------------------------
72 class EthernetSoC(BaseSoC
):
76 mem_map
.update(BaseSoC
.mem_map
)
78 def __init__(self
, **kwargs
):
79 BaseSoC
.__init
__(self
, **kwargs
)
81 # Ethernet ---------------------------------------------------------------------------------
83 self
.submodules
.ethphy
= LiteEthPHYRMII(
84 clock_pads
= self
.platform
.request("eth_clocks"),
85 pads
= self
.platform
.request("eth"))
86 self
.add_csr("ethphy")
88 self
.submodules
.ethmac
= LiteEthMAC(
91 interface
= "wishbone",
92 endianness
= self
.cpu
.endianness
)
93 self
.add_memory_region("ethmac", self
.mem_map
["ethmac"], 0x2000, type="io")
94 self
.add_wb_slave(self
.mem_map
["ethmac"], self
.ethmac
.bus
, 0x2000)
95 self
.add_csr("ethmac")
96 self
.add_interrupt("ethmac")
98 self
.platform
.add_period_constraint(self
.ethphy
.crg
.cd_eth_rx
.clk
, 1e9
/50e6
)
99 self
.platform
.add_period_constraint(self
.ethphy
.crg
.cd_eth_tx
.clk
, 1e9
/50e6
)
100 self
.platform
.add_false_path_constraints(
102 self
.ethphy
.crg
.cd_eth_rx
.clk
,
103 self
.ethphy
.crg
.cd_eth_tx
.clk
)
105 # Build --------------------------------------------------------------------------------------------
108 parser
= argparse
.ArgumentParser(description
="LiteX SoC on NeTV2")
110 soc_sdram_args(parser
)
111 parser
.add_argument("--with-ethernet", action
="store_true",
112 help="enable Ethernet support")
113 args
= parser
.parse_args()
115 cls
= EthernetSoC
if args
.with_ethernet
else BaseSoC
116 soc
= cls(**soc_sdram_argdict(args
))
117 builder
= Builder(soc
, **builder_argdict(args
))
121 if __name__
== "__main__":