litex/boards/targets/netv2.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # License: BSD
   5
   6 import argparse
   7
   8 from migen import *
   9
  10 from litex.boards.platforms import netv2
  11
  12 from litex.soc.cores.clock import *
  13 from litex.soc.integration.soc_sdram import *
  14 from litex.soc.integration.builder import *
  15
  16 from litedram.modules import MT41J128M16
  17 from litedram.phy import s7ddrphy
  18
  19 from liteeth.phy.rmii import LiteEthPHYRMII
  20 from liteeth.mac import LiteEthMAC
  21
  22 # CRG ----------------------------------------------------------------------------------------------
  23
  24 class _CRG(Module):
  25     def __init__(self, platform, sys_clk_freq):
  26         self.clock_domains.cd_sys = ClockDomain()
  27         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
  28         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
  29         self.clock_domains.cd_clk200 = ClockDomain()
  30         self.clock_domains.cd_clk100 = ClockDomain()
  31         self.clock_domains.cd_eth = ClockDomain()
  32
  33         # # #
  34
  35         self.cd_sys.clk.attr.add("keep")
  36         self.cd_sys4x.clk.attr.add("keep")
  37         self.cd_sys4x_dqs.clk.attr.add("keep")
  38
  39         self.submodules.pll = pll = S7PLL(speedgrade=-1)
  40         pll.register_clkin(platform.request("clk50"), 50e6)
  41         pll.create_clkout(self.cd_sys, sys_clk_freq)
  42         pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
  43         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
  44         pll.create_clkout(self.cd_clk200, 200e6)
  45         pll.create_clkout(self.cd_clk100, 100e6)
  46         pll.create_clkout(self.cd_eth, 50e6)
  47
  48         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
  49
  50 # BaseSoC ------------------------------------------------------------------------------------------
  51
  52 class BaseSoC(SoCSDRAM):
  53     def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
  54         platform = netv2.Platform()
  55         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
  56                          integrated_rom_size=integrated_rom_size,
  57                          integrated_sram_size=0x8000,
  58                          **kwargs)
  59
  60         self.submodules.crg = _CRG(platform, sys_clk_freq)
  61
  62         # sdram
  63         self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
  64         self.add_csr("ddrphy")
  65         sdram_module = MT41J128M16(sys_clk_freq, "1:4")
  66         self.register_sdram(self.ddrphy,
  67                             sdram_module.geom_settings,
  68                             sdram_module.timing_settings)
  69
  70 # EthernetSoC --------------------------------------------------------------------------------------
  71
  72 class EthernetSoC(BaseSoC):
  73     mem_map = {
  74         "ethmac": 0x30000000,  # (shadow @0xb0000000)
  75     }
  76     mem_map.update(BaseSoC.mem_map)
  77
  78     def __init__(self, **kwargs):
  79         BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
  80
  81         self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
  82                                                 self.platform.request("eth"))
  83         self.add_csr("ethphy")
  84         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
  85             interface="wishbone", endianness=self.cpu.endianness)
  86         self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
  87         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
  88         self.add_csr("ethmac")
  89         self.add_interrupt("ethmac")
  90
  91         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
  92         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
  93         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
  94         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
  95         self.platform.add_false_path_constraints(
  96             self.crg.cd_sys.clk,
  97             self.ethphy.crg.cd_eth_rx.clk,
  98             self.ethphy.crg.cd_eth_tx.clk)
  99
 100
 101 # Build --------------------------------------------------------------------------------------------
 102
 103 def main():
 104     parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2")
 105     builder_args(parser)
 106     soc_sdram_args(parser)
 107     parser.add_argument("--with-ethernet", action="store_true",
 108                         help="enable Ethernet support")
 109     args = parser.parse_args()
 110
 111     cls = EthernetSoC if args.with_ethernet else BaseSoC
 112     soc = cls(**soc_sdram_argdict(args))
 113     builder = Builder(soc, **builder_argdict(args))
 114     builder.build()
 115
 116
 117 if __name__ == "__main__":
 118     main()