litex/boards/targets/netv2.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # License: BSD
   5
   6 import argparse
   7
   8 from migen import *
   9
  10 from litex.boards.platforms import netv2
  11
  12 from litex.soc.cores.clock import *
  13 from litex.soc.integration.soc_sdram import *
  14 from litex.soc.integration.builder import *
  15
  16 from litedram.modules import K4B2G1646F
  17 from litedram.phy import s7ddrphy
  18
  19 from liteeth.phy.rmii import LiteEthPHYRMII
  20 from liteeth.mac import LiteEthMAC
  21
  22 # CRG ----------------------------------------------------------------------------------------------
  23
  24 class _CRG(Module):
  25     def __init__(self, platform, sys_clk_freq):
  26         self.clock_domains.cd_sys = ClockDomain()
  27         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
  28         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
  29         self.clock_domains.cd_clk200 = ClockDomain()
  30         self.clock_domains.cd_clk100 = ClockDomain()
  31         self.clock_domains.cd_eth = ClockDomain()
  32
  33         # # #
  34
  35         self.submodules.pll = pll = S7PLL(speedgrade=-1)
  36         pll.register_clkin(platform.request("clk50"), 50e6)
  37         pll.create_clkout(self.cd_sys, sys_clk_freq)
  38         pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
  39         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
  40         pll.create_clkout(self.cd_clk200, 200e6)
  41         pll.create_clkout(self.cd_clk100, 100e6)
  42         pll.create_clkout(self.cd_eth, 50e6)
  43
  44         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
  45
  46 # BaseSoC ------------------------------------------------------------------------------------------
  47
  48 class BaseSoC(SoCSDRAM):
  49     def __init__(self, sys_clk_freq=int(100e6), **kwargs):
  50         platform = netv2.Platform()
  51
  52         # SoCSDRAM ---------------------------------------------------------------------------------
  53         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
  54
  55         # CRG --------------------------------------------------------------------------------------
  56         self.submodules.crg = _CRG(platform, sys_clk_freq)
  57
  58         # DDR3 SDRAM -------------------------------------------------------------------------------
  59         if not self.integrated_main_ram_size:
  60             self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
  61                 memtype      = "DDR3",
  62                 nphases      = 4,
  63                 sys_clk_freq = sys_clk_freq)
  64             self.add_csr("ddrphy")
  65             sdram_module = K4B2G1646F(sys_clk_freq, "1:4")
  66             self.register_sdram(self.ddrphy,
  67                 geom_settings   = sdram_module.geom_settings,
  68                 timing_settings = sdram_module.timing_settings)
  69
  70 # EthernetSoC --------------------------------------------------------------------------------------
  71
  72 class EthernetSoC(BaseSoC):
  73     mem_map = {
  74         "ethmac": 0xb0000000,
  75     }
  76     mem_map.update(BaseSoC.mem_map)
  77
  78     def __init__(self, **kwargs):
  79         BaseSoC.__init__(self, **kwargs)
  80
  81         self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
  82                                                 self.platform.request("eth"))
  83         self.add_csr("ethphy")
  84         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
  85             interface="wishbone", endianness=self.cpu.endianness)
  86         self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
  87         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
  88         self.add_csr("ethmac")
  89         self.add_interrupt("ethmac")
  90
  91         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
  92         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
  93         self.platform.add_false_path_constraints(
  94             self.crg.cd_sys.clk,
  95             self.ethphy.crg.cd_eth_rx.clk,
  96             self.ethphy.crg.cd_eth_tx.clk)
  97
  98
  99 # Build --------------------------------------------------------------------------------------------
 100
 101 def main():
 102     parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2")
 103     builder_args(parser)
 104     soc_sdram_args(parser)
 105     parser.add_argument("--with-ethernet", action="store_true",
 106                         help="enable Ethernet support")
 107     args = parser.parse_args()
 108
 109     cls = EthernetSoC if args.with_ethernet else BaseSoC
 110     soc = cls(**soc_sdram_argdict(args))
 111     builder = Builder(soc, **builder_argdict(args))
 112     builder.build()
 113
 114
 115 if __name__ == "__main__":
 116     main()