3 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
10 from litex
.boards
.platforms
import netv2
12 from litex
.soc
.cores
.clock
import *
13 from litex
.soc
.integration
.soc_sdram
import *
14 from litex
.soc
.integration
.builder
import *
16 from litedram
.modules
import MT41J128M16
17 from litedram
.phy
import s7ddrphy
19 from liteeth
.phy
.rmii
import LiteEthPHYRMII
20 from liteeth
.mac
import LiteEthMAC
22 # CRG ----------------------------------------------------------------------------------------------
25 def __init__(self
, platform
, sys_clk_freq
):
26 self
.clock_domains
.cd_sys
= ClockDomain()
27 self
.clock_domains
.cd_sys4x
= ClockDomain(reset_less
=True)
28 self
.clock_domains
.cd_sys4x_dqs
= ClockDomain(reset_less
=True)
29 self
.clock_domains
.cd_clk200
= ClockDomain()
30 self
.clock_domains
.cd_eth
= ClockDomain()
34 self
.cd_sys
.clk
.attr
.add("keep")
35 self
.cd_sys4x
.clk
.attr
.add("keep")
36 self
.cd_sys4x_dqs
.clk
.attr
.add("keep")
38 self
.submodules
.pll
= pll
= S7PLL(speedgrade
=-1)
39 pll
.register_clkin(platform
.request("clk50"), 50e6
)
40 pll
.create_clkout(self
.cd_sys
, sys_clk_freq
)
41 pll
.create_clkout(self
.cd_sys4x
, 4*sys_clk_freq
)
42 pll
.create_clkout(self
.cd_sys4x_dqs
, 4*sys_clk_freq
, phase
=90)
43 pll
.create_clkout(self
.cd_clk200
, 200e6
)
44 pll
.create_clkout(self
.cd_eth
, 50e6
)
46 self
.submodules
.idelayctrl
= S7IDELAYCTRL(self
.cd_clk200
)
48 # BaseSoC ------------------------------------------------------------------------------------------
50 class BaseSoC(SoCSDRAM
):
51 def __init__(self
, sys_clk_freq
=int(100e6
), **kwargs
):
52 platform
= netv2
.Platform()
53 SoCSDRAM
.__init
__(self
, platform
, clk_freq
=sys_clk_freq
,
54 integrated_rom_size
=0x8000,
55 integrated_sram_size
=0x8000,
58 self
.submodules
.crg
= _CRG(platform
, sys_clk_freq
)
61 self
.submodules
.ddrphy
= s7ddrphy
.A7DDRPHY(platform
.request("ddram"), sys_clk_freq
=sys_clk_freq
)
62 self
.add_csr("ddrphy")
63 sdram_module
= MT41J128M16(sys_clk_freq
, "1:4")
64 self
.register_sdram(self
.ddrphy
,
65 sdram_module
.geom_settings
,
66 sdram_module
.timing_settings
)
68 # EthernetSoC --------------------------------------------------------------------------------------
70 class EthernetSoC(BaseSoC
):
72 "ethmac": 0x30000000, # (shadow @0xb0000000)
74 mem_map
.update(BaseSoC
.mem_map
)
76 def __init__(self
, **kwargs
):
77 BaseSoC
.__init
__(self
, **kwargs
)
79 self
.submodules
.ethphy
= LiteEthPHYRMII(self
.platform
.request("eth_clocks"),
80 self
.platform
.request("eth"))
81 self
.add_csr("ethphy")
82 self
.submodules
.ethmac
= LiteEthMAC(phy
=self
.ethphy
, dw
=32,
83 interface
="wishbone", endianness
=self
.cpu
.endianness
)
84 self
.add_wb_slave(self
.mem_map
["ethmac"], self
.ethmac
.bus
, 0x2000)
85 self
.add_memory_region("ethmac", self
.mem_map
["ethmac"] | self
.shadow_base
, 0x2000)
86 self
.add_csr("ethmac")
87 self
.add_interrupt("ethmac")
89 self
.ethphy
.crg
.cd_eth_rx
.clk
.attr
.add("keep")
90 self
.ethphy
.crg
.cd_eth_tx
.clk
.attr
.add("keep")
91 self
.platform
.add_period_constraint(self
.ethphy
.crg
.cd_eth_rx
.clk
, 1e9
/12.5e6
)
92 self
.platform
.add_period_constraint(self
.ethphy
.crg
.cd_eth_tx
.clk
, 1e9
/12.5e6
)
93 self
.platform
.add_false_path_constraints(
95 self
.ethphy
.crg
.cd_eth_rx
.clk
,
96 self
.ethphy
.crg
.cd_eth_tx
.clk
)
99 # Build --------------------------------------------------------------------------------------------
102 parser
= argparse
.ArgumentParser(description
="LiteX SoC on NeTV2")
104 soc_sdram_args(parser
)
105 parser
.add_argument("--with-ethernet", action
="store_true",
106 help="enable Ethernet support")
107 args
= parser
.parse_args()
109 cls
= EthernetSoC
if args
.with_ethernet
else BaseSoC
110 soc
= cls(**soc_sdram_argdict(args
))
111 builder
= Builder(soc
, **builder_argdict(args
))
115 if __name__
== "__main__":