litex/boards/targets/nexys_video.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # License: BSD
   5
   6 import argparse
   7
   8 from migen import *
   9
  10 from litex.boards.platforms import nexys_video
  11
  12 from litex.soc.cores.clock import *
  13 from litex.soc.integration.soc_core import mem_decoder
  14 from litex.soc.integration.soc_sdram import *
  15 from litex.soc.integration.builder import *
  16
  17 from litedram.modules import MT41K256M16
  18 from litedram.phy import s7ddrphy
  19
  20 from liteeth.phy.s7rgmii import LiteEthPHYRGMII
  21 from liteeth.core.mac import LiteEthMAC
  22
  23 # CRG ----------------------------------------------------------------------------------------------
  24
  25 class _CRG(Module):
  26     def __init__(self, platform, sys_clk_freq):
  27         self.clock_domains.cd_sys = ClockDomain()
  28         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
  29         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
  30         self.clock_domains.cd_clk200 = ClockDomain()
  31         self.clock_domains.cd_clk100 = ClockDomain()
  32
  33         # # #
  34
  35         self.cd_sys.clk.attr.add("keep")
  36         self.cd_sys4x.clk.attr.add("keep")
  37         self.cd_sys4x_dqs.clk.attr.add("keep")
  38
  39         self.submodules.pll = pll = S7MMCM(speedgrade=-1)
  40         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
  41         pll.register_clkin(platform.request("clk100"), 100e6)
  42         pll.create_clkout(self.cd_sys, sys_clk_freq)
  43         pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
  44         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
  45         pll.create_clkout(self.cd_clk200, 200e6)
  46
  47         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
  48
  49 # BaseSoC ------------------------------------------------------------------------------------------
  50
  51 class BaseSoC(SoCSDRAM):
  52     def __init__(self, sys_clk_freq=int(100e6), **kwargs):
  53         platform = nexys_video.Platform()
  54         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
  55                          integrated_rom_size=0x8000,
  56                          integrated_sram_size=0x8000,
  57                          **kwargs)
  58
  59         self.submodules.crg = _CRG(platform, sys_clk_freq)
  60
  61         # sdram
  62         self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
  63         self.add_csr("ddrphy")
  64         sdram_module = MT41K256M16(sys_clk_freq, "1:4")
  65         self.register_sdram(self.ddrphy,
  66                             sdram_module.geom_settings,
  67                             sdram_module.timing_settings)
  68
  69 # EthernetSoC --------------------------------------------------------------------------------------
  70
  71 class EthernetSoC(BaseSoC):
  72     mem_map = {
  73         "ethmac": 0x30000000,  # (shadow @0xb0000000)
  74     }
  75     mem_map.update(BaseSoC.mem_map)
  76
  77     def __init__(self, **kwargs):
  78         BaseSoC.__init__(self, **kwargs)
  79
  80         self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
  81                                                  self.platform.request("eth"))
  82         self.add_csr("ethphy")
  83         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
  84             interface="wishbone", endianness=self.cpu.endianness)
  85         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
  86         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
  87         self.add_csr("ethmac")
  88         self.add_interrupt("ethmac")
  89
  90         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
  91         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
  92         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
  93         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
  94         self.platform.add_false_path_constraints(
  95             self.crg.cd_sys.clk,
  96             self.ethphy.crg.cd_eth_rx.clk,
  97             self.ethphy.crg.cd_eth_tx.clk)
  98
  99 # Build --------------------------------------------------------------------------------------------
 100
 101 def main():
 102     parser = argparse.ArgumentParser(description="LiteX SoC on Nexys Video")
 103     builder_args(parser)
 104     soc_sdram_args(parser)
 105     parser.add_argument("--with-ethernet", action="store_true",
 106                         help="enable Ethernet support")
 107     args = parser.parse_args()
 108
 109     cls = EthernetSoC if args.with_ethernet else BaseSoC
 110     soc = cls(**soc_sdram_argdict(args))
 111     builder = Builder(soc, **builder_argdict(args))
 112     builder.build()
 113
 114
 115 if __name__ == "__main__":
 116     main()