litex/boards/targets/nexys_video.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # License: BSD
   5
   6 import argparse
   7
   8 from migen import *
   9
  10 from litex.boards.platforms import nexys_video
  11
  12 from litex.soc.cores.clock import *
  13 from litex.soc.integration.soc_core import *
  14 from litex.soc.integration.soc_sdram import *
  15 from litex.soc.integration.builder import *
  16
  17 from litedram.modules import MT41K256M16
  18 from litedram.phy import s7ddrphy
  19
  20 from liteeth.phy.s7rgmii import LiteEthPHYRGMII
  21
  22 # CRG ----------------------------------------------------------------------------------------------
  23
  24 class _CRG(Module):
  25     def __init__(self, platform, sys_clk_freq):
  26         self.clock_domains.cd_sys       = ClockDomain()
  27         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
  28         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
  29         self.clock_domains.cd_clk200    = ClockDomain()
  30         self.clock_domains.cd_clk100    = ClockDomain()
  31
  32         # # #
  33
  34         self.submodules.pll = pll = S7MMCM(speedgrade=-1)
  35         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
  36         pll.register_clkin(platform.request("clk100"), 100e6)
  37         pll.create_clkout(self.cd_sys,       sys_clk_freq)
  38         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
  39         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
  40         pll.create_clkout(self.cd_clk200,    200e6)
  41         pll.create_clkout(self.cd_clk100,    100e6)
  42
  43         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
  44
  45 # BaseSoC ------------------------------------------------------------------------------------------
  46
  47 class BaseSoC(SoCCore):
  48     def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
  49         platform = nexys_video.Platform()
  50
  51         # SoCCore ----------------------------------------------------------------------------------
  52         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
  53
  54         # CRG --------------------------------------------------------------------------------------
  55         self.submodules.crg = _CRG(platform, sys_clk_freq)
  56
  57         # DDR3 SDRAM -------------------------------------------------------------------------------
  58         if not self.integrated_main_ram_size:
  59             self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
  60                 memtype      = "DDR3",
  61                 nphases      = 4,
  62                 sys_clk_freq = sys_clk_freq)
  63             self.add_csr("ddrphy")
  64             self.add_sdram("sdram",
  65                 phy                     = self.ddrphy,
  66                 module                  = MT41K256M16(sys_clk_freq, "1:4"),
  67                 origin                  = self.mem_map["main_ram"],
  68                 size                    = kwargs.get("max_sdram_size", 0x40000000),
  69                 l2_cache_size           = kwargs.get("l2_size", 8192),
  70                 l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
  71                 l2_cache_reverse        = True
  72             )
  73
  74         # Ethernet ---------------------------------------------------------------------------------
  75         if with_ethernet:
  76             self.submodules.ethphy = LiteEthPHYRGMII(
  77                 clock_pads = self.platform.request("eth_clocks"),
  78                 pads       = self.platform.request("eth"))
  79             self.add_csr("ethphy")
  80             self.add_ethernet(phy=self.ethphy)
  81
  82 # Build --------------------------------------------------------------------------------------------
  83
  84 def main():
  85     parser = argparse.ArgumentParser(description="LiteX SoC on Nexys Video")
  86     builder_args(parser)
  87     soc_sdram_args(parser)
  88     parser.add_argument("--with-ethernet", action="store_true",
  89                         help="enable Ethernet support")
  90     args = parser.parse_args()
  91
  92     soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
  93     builder = Builder(soc, **builder_argdict(args))
  94     builder.build()
  95
  96
  97 if __name__ == "__main__":
  98     main()