litex/boards/targets/pcie_screamer.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # License: BSD
   5
   6 import argparse
   7
   8 from migen import *
   9
  10 from litex.boards.platforms import pcie_screamer
  11 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
  12
  13 from litex.soc.cores.clock import *
  14 from litex.soc.integration.soc_sdram import *
  15 from litex.soc.integration.builder import *
  16
  17 from litedram.modules import MT41K128M16
  18 from litedram.phy import s7ddrphy
  19
  20 # CRG ----------------------------------------------------------------------------------------------
  21
  22 class _CRG(Module):
  23     def __init__(self, platform, sys_clk_freq):
  24         self.clock_domains.cd_sys       = ClockDomain()
  25         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
  26         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
  27         self.clock_domains.cd_clk200    = ClockDomain()
  28         # # #
  29
  30         self.submodules.pll = pll = S7PLL(speedgrade=-1)
  31         pll.register_clkin(platform.request("clk100"), 100e6)
  32         pll.create_clkout(self.cd_sys,       sys_clk_freq)
  33         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
  34         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
  35         pll.create_clkout(self.cd_clk200,    200e6)
  36
  37         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
  38
  39 # BaseSoC ------------------------------------------------------------------------------------------
  40
  41 class BaseSoC(SoCSDRAM):
  42     def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
  43         platform = pcie_screamer.Platform()
  44
  45         # SoCSDRAM ---------------------------------------------------------------------------------
  46         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
  47             integrated_rom_size=integrated_rom_size,
  48             integrated_sram_size=0x8000,
  49             **kwargs)
  50
  51         # CRG --------------------------------------------------------------------------------------
  52         self.submodules.crg = _CRG(platform, sys_clk_freq)
  53
  54         # DDR3 SDRAM -------------------------------------------------------------------------------
  55         if not self.integrated_main_ram_size:
  56             self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
  57                 memtype      = "DDR3",
  58                 nphases      = 4,
  59                 sys_clk_freq = sys_clk_freq)
  60             self.add_csr("ddrphy")
  61             sdram_module = MT41K128M16(sys_clk_freq, "1:4")
  62             self.register_sdram(self.ddrphy,
  63                 geom_settings   = sdram_module.geom_settings,
  64                 timing_settings = sdram_module.timing_settings)
  65
  66 # Build --------------------------------------------------------------------------------------------
  67
  68 def main():
  69     parser = argparse.ArgumentParser(description="LiteX SoC on PCIe Screamer")
  70     builder_args(parser)
  71     soc_sdram_args(parser)
  72     vivado_build_args(parser)
  73     args = parser.parse_args()
  74
  75     soc = BaseSoC(**soc_sdram_argdict(args))
  76     builder = Builder(soc, **builder_argdict(args))
  77     builder.build(**vivado_build_argdict(args))
  78
  79
  80 if __name__ == "__main__":
  81     main()