litex/boards/targets/ulx3s.py

   1 #!/usr/bin/env python3
   2
   3 import argparse
   4
   5 from migen import *
   6 from migen.genlib.resetsync import AsyncResetSynchronizer
   7
   8 from litex.boards.platforms import ulx3s
   9
  10 from litex.soc.cores.clock import *
  11 from litex.soc.integration.soc_sdram import *
  12 from litex.soc.integration.builder import *
  13
  14 from litedram.modules import MT48LC16M16
  15 from litedram.phy import GENSDRPHY
  16
  17
  18 class _CRG(Module):
  19     def __init__(self, platform):
  20         self.clock_domains.cd_sys = ClockDomain()
  21         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
  22
  23         # # #
  24
  25         # clk / rst
  26         clk25 = platform.request("clk25")
  27         rst = platform.request("rst")
  28
  29         # pll
  30         self.submodules.pll = pll = ECP5PLL()
  31         self.comb += pll.reset.eq(rst)
  32         pll.register_clkin(clk25, 25e6)
  33         pll.create_clkout(self.cd_sys, 50e6, phase=11)
  34         pll.create_clkout(self.cd_sys_ps, 50e6, phase=20)
  35         # FIXME: AsyncResetSynchronizer needs FD1S3BX support.
  36         #self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
  37         self.comb += self.cd_sys.rst.eq(rst)
  38         platform.add_period_constraint(self.cd_sys.clk, 20.0)
  39         platform.add_period_constraint(self.cd_sys_ps.clk, 20.0)
  40
  41         # sdram clock
  42         self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
  43
  44         # Stop ESP32 from resetting FPGA
  45         wifi_gpio0 = platform.request("wifi_gpio0")
  46         self.comb += wifi_gpio0.eq(1)
  47
  48
  49 class BaseSoC(SoCSDRAM):
  50     def __init__(self, **kwargs):
  51         platform = ulx3s.Platform(toolchain="trellis")
  52         sys_clk_freq = int(50e6)
  53         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
  54                           integrated_rom_size=0x8000,
  55                           **kwargs)
  56
  57         self.submodules.crg = _CRG(platform)
  58
  59         if not self.integrated_main_ram_size:
  60             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
  61             sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
  62             self.register_sdram(self.sdrphy,
  63                                 sdram_module.geom_settings,
  64                                 sdram_module.timing_settings)
  65
  66 def main():
  67     parser = argparse.ArgumentParser(description="LiteX SoC port to the ULX3S")
  68     builder_args(parser)
  69     soc_sdram_args(parser)
  70     args = parser.parse_args()
  71
  72     soc = BaseSoC(**soc_sdram_argdict(args))
  73     builder = Builder(soc, **builder_argdict(args))
  74     builder.build()
  75
  76 if __name__ == "__main__":
  77     main()