litex/boards/targets/ulx3s.py

   1 #!/usr/bin/env python3
   2
   3 import argparse
   4
   5 from migen import *
   6 from migen.genlib.resetsync import AsyncResetSynchronizer
   7
   8 from litex.boards.platforms import ulx3s
   9
  10 from litex.soc.integration.soc_sdram import *
  11 from litex.soc.integration.builder import *
  12
  13 from litedram.modules import MT48LC16M16
  14 from litedram.phy import GENSDRPHY
  15 from litedram.core.controller import ControllerSettings
  16
  17
  18 class _CRG(Module):
  19     def __init__(self, platform):
  20         self.clock_domains.cd_sys = ClockDomain()
  21         self.clock_domains.cd_sys_ps = ClockDomain()
  22
  23         # # #
  24
  25         clk25 = platform.request("clk25")
  26         rst = platform.request("rst")
  27
  28         # sys_clk
  29         self.comb += self.cd_sys.clk.eq(clk25)
  30         # FIXME: AsyncResetSynchronizer needs FD1S3BX support.
  31         #self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
  32         self.comb += self.cd_sys.rst.eq(rst)
  33
  34         # sys_clk phase shifted (for sdram)
  35         sdram_ps_clk = self.cd_sys.clk
  36         # FIXME: phase shift with luts, needs PLL support.
  37         sdram_ps_luts = 5
  38         for i in range(sdram_ps_luts):
  39             new_sdram_ps_clk = Signal()
  40             self.specials += Instance("LUT4",
  41                 p_INIT=2,
  42                 i_A=sdram_ps_clk,
  43                 i_B=0,
  44                 i_C=0,
  45                 i_D=0,
  46                 o_Z=new_sdram_ps_clk)
  47             sdram_ps_clk = new_sdram_ps_clk
  48         self.comb += self.cd_sys_ps.clk.eq(sdram_ps_clk)
  49         sdram_clock = platform.request("sdram_clock")
  50         self.comb += sdram_clock.eq(sdram_ps_clk)
  51
  52         # Stop ESP32 from resetting FPGA
  53         wifi_gpio0 = platform.request("wifi_gpio0")
  54         self.comb += wifi_gpio0.eq(1)
  55
  56
  57 class BaseSoC(SoCSDRAM):
  58     def __init__(self, **kwargs):
  59         platform = ulx3s.Platform(toolchain="trellis")
  60         sys_clk_freq = int(25e6)
  61         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
  62                           l2_size=32,
  63                           integrated_rom_size=0x8000,
  64                           **kwargs)
  65
  66         self.submodules.crg = _CRG(platform)
  67
  68         if not self.integrated_main_ram_size:
  69             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
  70             sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
  71             self.register_sdram(self.sdrphy,
  72                                 sdram_module.geom_settings,
  73                                 sdram_module.timing_settings,
  74                                 controller_settings=ControllerSettings(
  75                                     with_refresh=False)) # FIXME
  76
  77
  78 def main():
  79     parser = argparse.ArgumentParser(description="LiteX SoC port to the ULX3S")
  80     builder_args(parser)
  81     soc_sdram_args(parser)
  82     args = parser.parse_args()
  83
  84     soc = BaseSoC(**soc_sdram_argdict(args))
  85     builder = Builder(soc, **builder_argdict(args))
  86     builder.build()
  87
  88
  89 if __name__ == "__main__":
  90     main()