litex/boards/targets/ulx3s.py

   1 #!/usr/bin/env python3
   2
   3 import argparse
   4
   5 from migen import *
   6 from migen.genlib.resetsync import AsyncResetSynchronizer
   7
   8 from litex.boards.platforms import ulx3s
   9
  10 from litex.soc.cores.clock import *
  11 from litex.soc.integration.soc_sdram import *
  12 from litex.soc.integration.builder import *
  13
  14 from litedram.modules import MT48LC16M16
  15 from litedram.phy import GENSDRPHY
  16
  17 # CRG ----------------------------------------------------------------------------------------------
  18
  19 class _CRG(Module):
  20     def __init__(self, platform):
  21         self.clock_domains.cd_sys = ClockDomain()
  22         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
  23
  24         # # #
  25
  26         self.cd_sys.clk.attr.add("keep")
  27         self.cd_sys_ps.clk.attr.add("keep")
  28
  29         # clk / rst
  30         clk25 = platform.request("clk25")
  31         rst = platform.request("rst")
  32         platform.add_period_constraint(clk25, 40.0)
  33
  34         # pll
  35         self.submodules.pll = pll = ECP5PLL()
  36         self.comb += pll.reset.eq(rst)
  37         pll.register_clkin(clk25, 25e6)
  38         pll.create_clkout(self.cd_sys, 50e6, phase=11)
  39         pll.create_clkout(self.cd_sys_ps, 50e6, phase=20)
  40         self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
  41
  42         # sdram clock
  43         self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
  44
  45         # Stop ESP32 from resetting FPGA
  46         wifi_gpio0 = platform.request("wifi_gpio0")
  47         self.comb += wifi_gpio0.eq(1)
  48
  49 # BaseSoC ------------------------------------------------------------------------------------------
  50
  51 class BaseSoC(SoCSDRAM):
  52     def __init__(self, platform, **kwargs):
  53         sys_clk_freq = int(50e6)
  54         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
  55                           integrated_rom_size=0x8000,
  56                           **kwargs)
  57
  58         self.submodules.crg = _CRG(platform)
  59
  60         if not self.integrated_main_ram_size:
  61             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
  62             sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
  63             self.register_sdram(self.sdrphy,
  64                                 sdram_module.geom_settings,
  65                                 sdram_module.timing_settings)
  66
  67 # Build --------------------------------------------------------------------------------------------
  68
  69 def main():
  70     parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
  71     parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
  72         help='gateware toolchain to use, diamond (default) or  trellis')
  73     parser.add_argument("--device", dest="device", default="LFE5U-45F",
  74         help='FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F')
  75     builder_args(parser)
  76     soc_sdram_args(parser)
  77     args = parser.parse_args()
  78
  79     platform = ulx3s.Platform(device=args.device, toolchain=args.toolchain)
  80     soc = BaseSoC(platform, **soc_sdram_argdict(args))
  81     builder = Builder(soc, **builder_argdict(args))
  82     builder.build()
  83
  84 if __name__ == "__main__":
  85     main()