litex/boards/targets/ulx3s.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # This file is Copyright (c) 2018 David Shah <dave@ds0.me>
   5 # License: BSD
   6
   7 import argparse
   8
   9 from migen import *
  10 from migen.genlib.resetsync import AsyncResetSynchronizer
  11
  12 from litex.boards.platforms import ulx3s
  13
  14 from litex.soc.cores.clock import *
  15 from litex.soc.integration.soc_sdram import *
  16 from litex.soc.integration.builder import *
  17
  18 from litedram.modules import MT48LC16M16
  19 from litedram.phy import GENSDRPHY
  20
  21 # CRG ----------------------------------------------------------------------------------------------
  22
  23 class _CRG(Module):
  24     def __init__(self, platform, sys_clk_freq):
  25         self.clock_domains.cd_sys = ClockDomain()
  26         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
  27
  28         # # #
  29
  30         self.cd_sys.clk.attr.add("keep")
  31         self.cd_sys_ps.clk.attr.add("keep")
  32
  33         # clk / rst
  34         clk25 = platform.request("clk25")
  35         rst = platform.request("rst")
  36         platform.add_period_constraint(clk25, 40.0)
  37
  38         # pll
  39         self.submodules.pll = pll = ECP5PLL()
  40         self.comb += pll.reset.eq(rst)
  41         pll.register_clkin(clk25, 25e6)
  42         pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11)
  43         pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20)
  44         self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
  45
  46         # sdram clock
  47         self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
  48
  49         # Stop ESP32 from resetting FPGA
  50         wifi_gpio0 = platform.request("wifi_gpio0")
  51         self.comb += wifi_gpio0.eq(1)
  52
  53 # BaseSoC ------------------------------------------------------------------------------------------
  54
  55 class BaseSoC(SoCSDRAM):
  56     def __init__(self, device="LFE5U-45F", toolchain="diamond", **kwargs):
  57         platform = ulx3s.Platform(device=device, toolchain=toolchain)
  58         sys_clk_freq = int(50e6)
  59         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
  60                           integrated_rom_size=0x8000,
  61                           **kwargs)
  62
  63         self.submodules.crg = _CRG(platform, sys_clk_freq)
  64
  65         if not self.integrated_main_ram_size:
  66             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=3)
  67             sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
  68             self.register_sdram(self.sdrphy,
  69                                 sdram_module.geom_settings,
  70                                 sdram_module.timing_settings)
  71
  72 # Build --------------------------------------------------------------------------------------------
  73
  74 def main():
  75     parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
  76     parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
  77         help='gateware toolchain to use, diamond (default) or  trellis')
  78     parser.add_argument("--device", dest="device", default="LFE5U-45F",
  79         help='FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F')
  80     builder_args(parser)
  81     soc_sdram_args(parser)
  82     args = parser.parse_args()
  83
  84     soc = BaseSoC(device=args.device, toolchain=args.toolchain, **soc_sdram_argdict(args))
  85     builder = Builder(soc, **builder_argdict(args))
  86     builder.build()
  87
  88 if __name__ == "__main__":
  89     main()