litex/boards/targets/ulx3s.py

   1 #!/usr/bin/env python3
   2
   3 import argparse
   4
   5 from migen import *
   6 from migen.genlib.resetsync import AsyncResetSynchronizer
   7
   8 from litex.boards.platforms import ulx3s
   9
  10 from litex.soc.integration.soc_sdram import *
  11 from litex.soc.integration.builder import *
  12
  13 from litedram.modules import MT48LC16M16
  14 from litedram.phy import GENSDRPHY
  15
  16
  17 class _CRG(Module):
  18     def __init__(self, platform):
  19         self.clock_domains.cd_sys = ClockDomain()
  20         self.clock_domains.cd_sys_ps = ClockDomain()
  21
  22         # # #
  23
  24         clk25 = platform.request("clk25")
  25         rst = platform.request("rst")
  26
  27         # sys_clk
  28         # FIXME: AsyncResetSynchronizer needs FD1S3BX support.
  29         #self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
  30         self.comb += self.cd_sys.rst.eq(rst)
  31         self.comb += self.cd_sys_ps.rst.eq(rst)
  32
  33         sys_clk = Signal()
  34         sdram_ps_clk = Signal()
  35
  36         self.specials += Instance(
  37             "EHXPLLL",
  38             i_CLKI=clk25,
  39             i_CLKFB=sys_clk,
  40             i_PHASESEL1=0,
  41             i_PHASESEL0=0,
  42             i_PHASEDIR=0,
  43             i_PHASESTEP=0,
  44             i_PHASELOADREG=0,
  45             i_STDBY=0,
  46             i_PLLWAKESYNC=0,
  47             i_RST=0,
  48             i_ENCLKOP=0,
  49             i_ENCLKOS=0,
  50             o_CLKOP=sys_clk,
  51             o_CLKOS=sdram_ps_clk,
  52             p_CLKOS_FPHASE=2,
  53             p_CLKOS_CPHASE=15,
  54             p_CLKOP_FPHASE=0,
  55             p_CLKOP_CPHASE=12,
  56             p_PLL_LOCK_MODE=0,
  57             p_OUTDIVIDER_MUXB="DIVB",
  58             p_CLKOS_ENABLE="ENABLED",
  59             p_CLKOP_ENABLE="ENABLED",
  60             p_CLKOS_DIV=13,
  61             p_CLKOP_DIV=13,
  62             p_CLKFB_DIV=2,
  63             p_CLKI_DIV=1,
  64             p_FEEDBK_PATH="CLKOP",
  65             attr=[("ICP_CURRENT", "6"), ("LPF_RESISTOR", "16"), ("MFG_ENABLE_FILTEROPAMP", "1"), ("MFG_GMCREF_SEL", "2")]
  66         )
  67
  68         self.comb += self.cd_sys.clk.eq(sys_clk)
  69         self.comb += self.cd_sys_ps.clk.eq(sdram_ps_clk)
  70         sdram_clock = platform.request("sdram_clock")
  71         self.comb += sdram_clock.eq(sys_clk)
  72
  73         # Stop ESP32 from resetting FPGA
  74         wifi_gpio0 = platform.request("wifi_gpio0")
  75         self.comb += wifi_gpio0.eq(1)
  76
  77         ext0p = platform.request("ext0p")
  78         self.comb += ext0p.eq(sdram_ps_clk)
  79         ext1p = platform.request("ext1p")
  80         self.comb += ext1p.eq(self.cd_sys.clk)
  81
  82
  83 class BaseSoC(SoCSDRAM):
  84     def __init__(self, **kwargs):
  85         platform = ulx3s.Platform(toolchain="prjtrellis")
  86         sys_clk_freq = int(50e6)
  87         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
  88                           l2_size=32,
  89                           integrated_rom_size=0x8000,
  90                           **kwargs)
  91
  92         self.submodules.crg = _CRG(platform)
  93
  94         if not self.integrated_main_ram_size:
  95             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
  96             sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
  97             self.register_sdram(self.sdrphy,
  98                                 sdram_module.geom_settings,
  99                                 sdram_module.timing_settings)
 100
 101
 102 def main():
 103     parser = argparse.ArgumentParser(description="LiteX SoC port to the ULX3S")
 104     builder_args(parser)
 105     soc_sdram_args(parser)
 106     args = parser.parse_args()
 107
 108     soc = BaseSoC(**soc_sdram_argdict(args))
 109     builder = Builder(soc, **builder_argdict(args))
 110     builder.build()
 111
 112
 113 if __name__ == "__main__":
 114     main()