litex/build/xilinx/common.py

   1 import os
   2 import sys
   3 try:
   4     import colorama
   5     # install escape sequence translation on Windows
   6     if os.getenv("COLORAMA", "") == "force":
   7         colorama.init(strip=False)
   8     else:
   9         colorama.init()
  10     _have_colorama = True
  11 except ImportError:
  12     _have_colorama = False
  13
  14 from litex.gen.fhdl.structure import *
  15 from litex.gen.fhdl.specials import Instance
  16 from litex.gen.fhdl.module import Module
  17 from litex.gen.genlib.cdc import *
  18 from litex.gen.genlib.resetsync import AsyncResetSynchronizer
  19 from litex.gen.genlib.io import *
  20
  21 from litex.build import tools
  22
  23
  24 colors = []
  25 if _have_colorama:
  26     colors += [
  27         ("^ERROR:.*$", colorama.Fore.RED + colorama.Style.BRIGHT +
  28          r"\g<0>" + colorama.Style.RESET_ALL),
  29         ("^CRITICAL WARNING:.*$", colorama.Fore.RED +
  30          r"\g<0>" + colorama.Style.RESET_ALL),
  31         ("^WARNING:.*$", colorama.Fore.YELLOW +
  32          r"\g<0>" + colorama.Style.RESET_ALL),
  33         ("^INFO:.*$", colorama.Fore.GREEN +
  34          r"\g<0>" + colorama.Style.RESET_ALL),
  35     ]
  36
  37
  38 def settings(path, name=None, ver=None, first=None):
  39     if first == "version":
  40         if not ver:
  41             vers = tools.versions(path)
  42             ver = max(vers)
  43
  44         full = os.path.join(path, str(ver), name)
  45
  46     elif first == "name":
  47         path = os.path.join(path, name)
  48
  49         if not ver:
  50             vers = tools.versions(path)
  51             ver = max(vers)
  52
  53         full = os.path.join(path, str(ver))
  54
  55     if not vers:
  56         raise OSError(
  57             "no version directory for Xilinx tools found in {}".format(
  58                 path))
  59
  60     search = [64, 32]
  61     if tools.arch_bits() == 32:
  62         search = [32]
  63
  64     if sys.platform == "win32" or sys.platform == "cygwin":
  65         script_ext = "bat"
  66     else:
  67         script_ext = "sh"
  68
  69     searched_in = []
  70     for b in search:
  71         settings = os.path.join(full, "settings{0}.{1}".format(b, script_ext))
  72         if os.path.exists(settings):
  73             return settings
  74         searched_in.append(settings)
  75
  76     raise OSError(
  77         "no Xilinx tools settings file found.\n"
  78         "Looked in:\n"
  79         "   " +
  80         "\n   ".join(searched_in))
  81
  82
  83 class XilinxMultiRegImpl(MultiRegImpl):
  84     def __init__(self, *args, **kwargs):
  85         MultiRegImpl.__init__(self, *args, **kwargs)
  86         for r in self.regs:
  87             r.attr.add("async_reg")
  88             r.attr.add("no_shreg_extract")
  89
  90
  91 class XilinxMultiReg:
  92     @staticmethod
  93     def lower(dr):
  94         return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
  95
  96
  97 class XilinxAsyncResetSynchronizerImpl(Module):
  98     def __init__(self, cd, async_reset):
  99         if not hasattr(async_reset, "attr"):
 100             i, async_reset = async_reset, Signal()
 101             self.comb += async_reset.eq(i)
 102         rst_meta = Signal()
 103         self.specials += [
 104             Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset,
 105                 i_CE=1, i_C=cd.clk, o_Q=rst_meta,
 106                 attr={"async_reg", "ars_ff"}),
 107             Instance("FDPE", p_INIT=1, i_D=rst_meta, i_PRE=async_reset,
 108                 i_CE=1, i_C=cd.clk, o_Q=cd.rst,
 109                 attr={"async_reg", "ars_ff"})
 110         ]
 111         async_reset.attr.add("ars_false_path")
 112
 113
 114 class XilinxAsyncResetSynchronizer:
 115     @staticmethod
 116     def lower(dr):
 117         return XilinxAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
 118
 119
 120 class XilinxDifferentialInputImpl(Module):
 121     def __init__(self, i_p, i_n, o):
 122         self.specials += Instance("IBUFDS", i_I=i_p, i_IB=i_n, o_O=o)
 123
 124
 125 class XilinxDifferentialInput:
 126     @staticmethod
 127     def lower(dr):
 128         return XilinxDifferentialInputImpl(dr.i_p, dr.i_n, dr.o)
 129
 130
 131 class XilinxDifferentialOutputImpl(Module):
 132     def __init__(self, i, o_p, o_n):
 133         self.specials += Instance("OBUFDS", i_I=i, o_O=o_p, o_OB=o_n)
 134
 135
 136 class XilinxDifferentialOutput:
 137     @staticmethod
 138     def lower(dr):
 139         return XilinxDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
 140
 141
 142 class XilinxDDROutputImpl(Module):
 143     def __init__(self, i1, i2, o, clk):
 144         self.specials += Instance("ODDR2",
 145                 p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC",
 146                 i_C0=clk, i_C1=~clk, i_CE=1, i_S=0, i_R=0,
 147                 i_D0=i1, i_D1=i2, o_Q=o,
 148         )
 149
 150
 151 class XilinxDDROutput:
 152     @staticmethod
 153     def lower(dr):
 154         return XilinxDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
 155
 156
 157 xilinx_special_overrides = {
 158     MultiReg:               XilinxMultiReg,
 159     AsyncResetSynchronizer: XilinxAsyncResetSynchronizer,
 160     DifferentialInput:      XilinxDifferentialInput,
 161     DifferentialOutput:     XilinxDifferentialOutput,
 162     DDROutput:              XilinxDDROutput
 163 }
 164
 165
 166 class XilinxDDROutputImplS7(Module):
 167     def __init__(self, i1, i2, o, clk):
 168         self.specials += Instance("ODDR",
 169                 p_DDR_CLK_EDGE="SAME_EDGE",
 170                 i_C=clk, i_CE=1, i_S=0, i_R=0,
 171                 i_D1=i1, i_D2=i2, o_Q=o,
 172         )
 173
 174
 175 class XilinxDDROutputS7:
 176     @staticmethod
 177     def lower(dr):
 178         return XilinxDDROutputImplS7(dr.i1, dr.i2, dr.o, dr.clk)
 179
 180
 181 xilinx_s7_special_overrides = {
 182     DDROutput:              XilinxDDROutputS7
 183 }