litex/gen/fhdl/verilog.py

   1 from functools import partial
   2 from operator import itemgetter
   3 import collections
   4
   5 from litex.gen.fhdl.structure import *
   6 from litex.gen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
   7 from litex.gen.fhdl.tools import *
   8 from litex.gen.fhdl.namer import build_namespace
   9 from litex.gen.fhdl.conv_output import ConvOutput
  10
  11
  12 _reserved_keywords = {
  13     "always", "and", "assign", "automatic", "begin", "buf", "bufif0", "bufif1",
  14     "case", "casex", "casez", "cell", "cmos", "config", "deassign", "default",
  15     "defparam", "design", "disable", "edge", "else", "end", "endcase",
  16     "endconfig", "endfunction", "endgenerate", "endmodule", "endprimitive",
  17     "endspecify", "endtable", "endtask", "event", "for", "force", "forever",
  18     "fork", "function", "generate", "genvar", "highz0", "highz1", "if",
  19     "ifnone", "incdir", "include", "initial", "inout", "input",
  20     "instance", "integer", "join", "large", "liblist", "library", "localparam",
  21     "macromodule", "medium", "module", "nand", "negedge", "nmos", "nor",
  22     "noshowcancelled", "not", "notif0", "notif1", "or", "output", "parameter",
  23     "pmos", "posedge", "primitive", "pull0", "pull1" "pulldown",
  24     "pullup", "pulsestyle_onevent", "pulsestyle_ondetect", "remos", "real",
  25     "realtime", "reg", "release", "repeat", "rnmos", "rpmos", "rtran",
  26     "rtranif0", "rtranif1", "scalared", "showcancelled", "signed", "small",
  27     "specify", "specparam", "strong0", "strong1", "supply0", "supply1",
  28     "table", "task", "time", "tran", "tranif0", "tranif1", "tri", "tri0",
  29     "tri1", "triand", "trior", "trireg", "unsigned", "use", "vectored", "wait",
  30     "wand", "weak0", "weak1", "while", "wire", "wor","xnor", "xor", "do"
  31 }
  32
  33
  34 def _printsig(ns, s):
  35     if s.signed:
  36         n = "signed "
  37     else:
  38         n = ""
  39     if len(s) > 1:
  40         n += "[" + str(len(s)-1) + ":0] "
  41     n += ns.get_name(s)
  42     return n
  43
  44
  45 def _printconstant(node):
  46     if node.signed:
  47         return (str(node.nbits) + "'sd" + str(2**node.nbits + node.value),
  48                 True)
  49     else:
  50         return str(node.nbits) + "'d" + str(node.value), False
  51
  52
  53 def _printexpr(ns, node):
  54     if isinstance(node, Constant):
  55         return _printconstant(node)
  56     elif isinstance(node, Signal):
  57         return ns.get_name(node), node.signed
  58     elif isinstance(node, _Operator):
  59         arity = len(node.operands)
  60         r1, s1 = _printexpr(ns, node.operands[0])
  61         if arity == 1:
  62             if node.op == "-":
  63                 if s1:
  64                     r = node.op + r1
  65                 else:
  66                     r = "-$signed({1'd0, " + r1 + "})"
  67                 s = True
  68             else:
  69                 r = node.op + r1
  70                 s = s1
  71         elif arity == 2:
  72             r2, s2 = _printexpr(ns, node.operands[1])
  73             if node.op not in ["<<<", ">>>"]:
  74                 if s2 and not s1:
  75                     r1 = "$signed({1'd0, " + r1 + "})"
  76                 if s1 and not s2:
  77                     r2 = "$signed({1'd0, " + r2 + "})"
  78             r = r1 + " " + node.op + " " + r2
  79             s = s1 or s2
  80         elif arity == 3:
  81             assert node.op == "m"
  82             r2, s2 = _printexpr(ns, node.operands[1])
  83             r3, s3 = _printexpr(ns, node.operands[2])
  84             if s2 and not s3:
  85                 r3 = "$signed({1'd0, " + r3 + "})"
  86             if s3 and not s2:
  87                 r2 = "$signed({1'd0, " + r2 + "})"
  88             r = r1 + " ? " + r2 + " : " + r3
  89             s = s2 or s3
  90         else:
  91             raise TypeError
  92         return "(" + r + ")", s
  93     elif isinstance(node, _Slice):
  94         # Verilog does not like us slicing non-array signals...
  95         if isinstance(node.value, Signal) \
  96           and len(node.value) == 1 \
  97           and node.start == 0 and node.stop == 1:
  98               return _printexpr(ns, node.value)
  99
 100         if node.start + 1 == node.stop:
 101             sr = "[" + str(node.start) + "]"
 102         else:
 103             sr = "[" + str(node.stop-1) + ":" + str(node.start) + "]"
 104         r, s = _printexpr(ns, node.value)
 105         return r + sr, s
 106     elif isinstance(node, Cat):
 107         l = [_printexpr(ns, v)[0] for v in reversed(node.l)]
 108         return "{" + ", ".join(l) + "}", False
 109     elif isinstance(node, Replicate):
 110         return "{" + str(node.n) + "{" + _printexpr(ns, node.v)[0] + "}}", False
 111     else:
 112         raise TypeError("Expression of unrecognized type: '{}'".format(type(node).__name__))
 113
 114
 115 (_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)
 116
 117
 118 def _printnode(ns, at, level, node):
 119     if isinstance(node, Display):
 120         s = "\"" + node.s + "\\r\""
 121         for arg in node.args:
 122             s += ", "
 123             if isinstance(arg, Signal):
 124                 s += ns.get_name(arg)
 125             else:
 126                 s += str(arg)
 127         return "\t"*level + "$display(" + s + ");\n"
 128     elif isinstance(node, _Assign):
 129         if at == _AT_BLOCKING:
 130             assignment = " = "
 131         elif at == _AT_NONBLOCKING:
 132             assignment = " <= "
 133         elif is_variable(node.l):
 134             assignment = " = "
 135         else:
 136             assignment = " <= "
 137         return "\t"*level + _printexpr(ns, node.l)[0] + assignment + _printexpr(ns, node.r)[0] + ";\n"
 138     elif isinstance(node, collections.Iterable):
 139         return "".join(list(map(partial(_printnode, ns, at, level), node)))
 140     elif isinstance(node, If):
 141         r = "\t"*level + "if (" + _printexpr(ns, node.cond)[0] + ") begin\n"
 142         r += _printnode(ns, at, level + 1, node.t)
 143         if node.f:
 144             r += "\t"*level + "end else begin\n"
 145             r += _printnode(ns, at, level + 1, node.f)
 146         r += "\t"*level + "end\n"
 147         return r
 148     elif isinstance(node, Case):
 149         if node.cases:
 150             r = "\t"*level + "case (" + _printexpr(ns, node.test)[0] + ")\n"
 151             css = [(k, v) for k, v in node.cases.items() if isinstance(k, Constant)]
 152             css = sorted(css, key=lambda x: x[0].value)
 153             for choice, statements in css:
 154                 r += "\t"*(level + 1) + _printexpr(ns, choice)[0] + ": begin\n"
 155                 r += _printnode(ns, at, level + 2, statements)
 156                 r += "\t"*(level + 1) + "end\n"
 157             if "default" in node.cases:
 158                 r += "\t"*(level + 1) + "default: begin\n"
 159                 r += _printnode(ns, at, level + 2, node.cases["default"])
 160                 r += "\t"*(level + 1) + "end\n"
 161             r += "\t"*level + "endcase\n"
 162             return r
 163         else:
 164             return ""
 165     else:
 166         raise TypeError("Node of unrecognized type: "+str(type(node)))
 167
 168
 169 def _list_comb_wires(f):
 170     r = set()
 171     groups = group_by_targets(f.comb)
 172     for g in groups:
 173         if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
 174             r |= g[0]
 175     return r
 176
 177 def _printattr(sig, attr_translate):
 178     r = ""
 179     firsta = True
 180     for attr in sorted(sig.attr,
 181                        key=lambda x: ("", x) if isinstance(x, str) else x):
 182         if isinstance(attr, tuple):
 183             # platform-dependent attribute
 184             attr_name, attr_value = attr
 185         else:
 186             # translated attribute
 187             at = attr_translate[attr]
 188             if at is None:
 189                 continue
 190             attr_name, attr_value = at
 191         if not firsta:
 192             r += ", "
 193         firsta = False
 194         r += attr_name + " = \"" + attr_value + "\""
 195     if r:
 196         r = "(* " + r + " *)"
 197     return r
 198
 199
 200 def _printheader(f, ios, name, ns, attr_translate,
 201                  reg_initialization):
 202     sigs = list_signals(f) | list_special_ios(f, True, True, True)
 203     special_outs = list_special_ios(f, False, True, True)
 204     inouts = list_special_ios(f, False, False, True)
 205     targets = list_targets(f) | special_outs
 206     wires = _list_comb_wires(f) | special_outs
 207     r = "module " + name + "(\n"
 208     firstp = True
 209     for sig in sorted(ios, key=lambda x: x.duid):
 210         if not firstp:
 211             r += ",\n"
 212         firstp = False
 213         attr = _printattr(sig, attr_translate)
 214         if attr:
 215             r += "\t" + attr
 216         if sig in inouts:
 217             r += "\tinout " + _printsig(ns, sig)
 218         elif sig in targets:
 219             if sig in wires:
 220                 r += "\toutput " + _printsig(ns, sig)
 221             else:
 222                 r += "\toutput reg " + _printsig(ns, sig)
 223         else:
 224             r += "\tinput " + _printsig(ns, sig)
 225     r += "\n);\n\n"
 226     for sig in sorted(sigs - ios, key=lambda x: x.duid):
 227         attr = _printattr(sig, attr_translate)
 228         if attr:
 229             r += attr + " "
 230         if sig in wires:
 231             r += "wire " + _printsig(ns, sig) + ";\n"
 232         else:
 233             if reg_initialization:
 234                 r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
 235             else:
 236                 r += "reg " + _printsig(ns, sig) + ";\n"
 237     r += "\n"
 238     return r
 239
 240
 241 def _printcomb(f, ns,
 242                display_run,
 243                dummy_signal,
 244                blocking_assign):
 245     r = ""
 246     if f.comb:
 247         if dummy_signal:
 248             explanation = """
 249 // Adding a dummy event (using a dummy signal 'dummy_s') to get the simulator
 250 // to run the combinatorial process once at the beginning.
 251 """
 252             syn_off = "// synthesis translate_off\n"
 253             syn_on = "// synthesis translate_on\n"
 254             dummy_s = Signal(name_override="dummy_s")
 255             r += explanation
 256             r += syn_off
 257             r += "reg " + _printsig(ns, dummy_s) + ";\n"
 258             r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n"
 259             r += syn_on
 260             r += "\n"
 261
 262         groups = group_by_targets(f.comb)
 263
 264         for n, g in enumerate(groups):
 265             if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
 266                 r += "assign " + _printnode(ns, _AT_BLOCKING, 0, g[1][0])
 267             else:
 268                 if dummy_signal:
 269                     dummy_d = Signal(name_override="dummy_d")
 270                     r += "\n" + syn_off
 271                     r += "reg " + _printsig(ns, dummy_d) + ";\n"
 272                     r += syn_on
 273
 274                 r += "always @(*) begin\n"
 275                 if display_run:
 276                     r += "\t$display(\"Running comb block #" + str(n) + "\");\n"
 277                 if blocking_assign:
 278                     for t in g[0]:
 279                         r += "\t" + ns.get_name(t) + " = " + _printexpr(ns, t.reset)[0] + ";\n"
 280                     r += _printnode(ns, _AT_BLOCKING, 1, g[1])
 281                 else:
 282                     for t in g[0]:
 283                         r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n"
 284                     r += _printnode(ns, _AT_NONBLOCKING, 1, g[1])
 285                 if dummy_signal:
 286                     r += syn_off
 287                     r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
 288                     r += syn_on
 289                 r += "end\n"
 290     r += "\n"
 291     return r
 292
 293
 294 def _printsync(f, ns):
 295     r = ""
 296     for k, v in sorted(f.sync.items(), key=itemgetter(0)):
 297         r += "always @(posedge " + ns.get_name(f.clock_domains[k].clk) + ") begin\n"
 298         r += _printnode(ns, _AT_SIGNAL, 1, v)
 299         r += "end\n\n"
 300     return r
 301
 302
 303 def _printspecials(overrides, specials, ns, add_data_file):
 304     r = ""
 305     for special in sorted(specials, key=lambda x: x.duid):
 306         pr = call_special_classmethod(overrides, special, "emit_verilog", ns, add_data_file)
 307         if pr is None:
 308             raise NotImplementedError("Special " + str(special) + " failed to implement emit_verilog")
 309         r += pr
 310     return r
 311
 312
 313 class DummyAttrTranslate:
 314     def __getitem__(self, k):
 315         return (k, "true")
 316
 317
 318 def convert(f, ios=None, name="top",
 319   special_overrides=dict(),
 320   attr_translate=DummyAttrTranslate(),
 321   create_clock_domains=True,
 322   display_run=False,
 323   reg_initialization=True,
 324   dummy_signal=True,
 325   blocking_assign=False,
 326   regular_comb=True):
 327     r = ConvOutput()
 328     if not isinstance(f, _Fragment):
 329         f = f.get_fragment()
 330     if ios is None:
 331         ios = set()
 332
 333     for cd_name in sorted(list_clock_domains(f)):
 334         try:
 335             f.clock_domains[cd_name]
 336         except KeyError:
 337             if create_clock_domains:
 338                 cd = ClockDomain(cd_name)
 339                 f.clock_domains.append(cd)
 340                 ios |= {cd.clk, cd.rst}
 341             else:
 342                 print("available clock domains:")
 343                 for f in f.clock_domains:
 344                     print(f.name)
 345                 raise KeyError("Unresolved clock domain: '"+cd_name+"'")
 346
 347     f = lower_complex_slices(f)
 348     insert_resets(f)
 349     f = lower_basics(f)
 350     fs, lowered_specials = lower_specials(special_overrides, f.specials)
 351     f += lower_basics(fs)
 352
 353     for io in sorted(ios, key=lambda x: x.duid):
 354         if io.name_override is None:
 355             io_name = io.backtrace[-1][0]
 356             if io_name:
 357                 io.name_override = io_name
 358     ns = build_namespace(list_signals(f) \
 359         | list_special_ios(f, True, True, True) \
 360         | ios, _reserved_keywords)
 361     ns.clock_domains = f.clock_domains
 362     r.ns = ns
 363
 364     src = "/* Machine-generated using LiteX gen */\n"
 365     src += _printheader(f, ios, name, ns, attr_translate,
 366                         reg_initialization=reg_initialization)
 367     src += _printcomb(f, ns,
 368                       display_run=display_run,
 369                       dummy_signal=dummy_signal,
 370                       blocking_assign=blocking_assign)
 371     src += _printsync(f, ns)
 372     src += _printspecials(special_overrides, f.specials - lowered_specials, ns, r.add_data_file)
 373     src += "endmodule\n"
 374     r.set_main_source(src)
 375
 376     return r