litex/gen/migen/build/platforms/m1.py

   1 from migen.build.generic_platform import *
   2 from migen.build.xilinx import XilinxPlatform
   3 from migen.build.xilinx.programmer import UrJTAG
   4
   5
   6 _io = [
   7     ("user_led", 0, Pins("B16"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
   8     ("user_led", 1, Pins("A16"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
   9
  10     ("user_btn", 0, Pins("AB4"), IOStandard("LVCMOS33")),
  11     ("user_btn", 1, Pins("AA4"), IOStandard("LVCMOS33")),
  12     ("user_btn", 2, Pins("AB5"), IOStandard("LVCMOS33")),
  13
  14     ("clk50", 0, Pins("AB11"), IOStandard("LVCMOS33")),
  15
  16     # When executing softcore code in-place from the flash, we want
  17     # the flash reset to be released before the system reset.
  18     ("norflash_rst_n", 0, Pins("P22"), IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)),
  19     ("norflash", 0,
  20         Subsignal("adr", Pins("L22 L20 K22 K21 J19 H20 F22",
  21             "F21 K17 J17 E22 E20 H18 H19 F20",
  22             "G19 C22 C20 D22 D21 F19 F18 D20 D19")),
  23         Subsignal("d", Pins("AA20 U14 U13 AA6 AB6 W4 Y4 Y7",
  24             "AA2 AB2 V15 AA18 AB18 Y13 AA12 AB12"), Misc("PULLDOWN")),
  25         Subsignal("oe_n", Pins("M22")),
  26         Subsignal("we_n", Pins("N20")),
  27         Subsignal("ce_n", Pins("M21")),
  28         IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)
  29     ),
  30
  31     ("serial", 0,
  32         Subsignal("tx", Pins("L17"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")),
  33         Subsignal("rx", Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLUP"))
  34     ),
  35
  36     ("ddram_clock", 0,
  37         Subsignal("p", Pins("M3")),
  38         Subsignal("n", Pins("L4")),
  39         IOStandard("SSTL2_I")
  40     ),
  41     ("ddram", 0,
  42         Subsignal("a", Pins("B1 B2 H8 J7 E4 D5 K7 F5 G6 C1 C3 D1 D2")),
  43         Subsignal("ba", Pins("A2 E6")),
  44         Subsignal("cs_n", Pins("F7")),
  45         Subsignal("cke", Pins("G7")),
  46         Subsignal("ras_n", Pins("E5")),
  47         Subsignal("cas_n", Pins("C4")),
  48         Subsignal("we_n", Pins("D3")),
  49         Subsignal("dq", Pins("Y2 W3 W1 P8 P7 P6 P5 T4 T3",
  50             "U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4",
  51             "M5 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1")),
  52         Subsignal("dm", Pins("E1 E3 F3 G4")),
  53         Subsignal("dqs", Pins("F1 F2 H5 H6")),
  54         IOStandard("SSTL2_I")
  55     ),
  56
  57     ("eth_clocks", 0,
  58         Subsignal("phy", Pins("M20")),
  59         Subsignal("rx", Pins("H22")),
  60         Subsignal("tx", Pins("H21")),
  61         IOStandard("LVCMOS33")
  62     ),
  63     ("eth", 0,
  64         Subsignal("rst_n", Pins("R22")),
  65         Subsignal("dv", Pins("V21")),
  66         Subsignal("rx_er", Pins("V22")),
  67         Subsignal("rx_data", Pins("U22 U20 T22 T21")),
  68         Subsignal("tx_en", Pins("N19")),
  69         Subsignal("tx_er", Pins("M19")),
  70         Subsignal("tx_data", Pins("M16 L15 P19 P20")),
  71         Subsignal("col", Pins("W20")),
  72         Subsignal("crs", Pins("W22")),
  73         IOStandard("LVCMOS33")
  74     ),
  75
  76     ("vga_out", 0,
  77         Subsignal("clk", Pins("A11")),
  78         Subsignal("r", Pins("C6 B6 A6 C7 A7 B8 A8 D9")),
  79         Subsignal("g", Pins("C8 C9 A9 D7 D8 D10 C10 B10")),
  80         Subsignal("b", Pins("D11 C12 B12 A12 C13 A13 D14 C14")),
  81         Subsignal("hsync_n", Pins("A14")),
  82         Subsignal("vsync_n", Pins("C15")),
  83         Subsignal("psave_n", Pins("B14")),
  84         IOStandard("LVCMOS33")
  85     ),
  86
  87     ("mmc", 0,
  88         Subsignal("clk", Pins("A10")),
  89         Subsignal("cmd", Pins("B18")),
  90         Subsignal("dat", Pins("A18 E16 C17 A17")),
  91         IOStandard("LVCMOS33")
  92     ),
  93
  94     # Digital video mixer extension board
  95     ("dvi_in", 0,
  96         Subsignal("clk", Pins("A20")),
  97         Subsignal("data0_n", Pins("A21")),
  98         Subsignal("data1", Pins("B21")),
  99         Subsignal("data2_n", Pins("B22")),
 100         Subsignal("scl", Pins("G16")),
 101         Subsignal("sda", Pins("G17")),
 102         IOStandard("LVCMOS33")
 103     ),
 104     ("dvi_in", 1,
 105         Subsignal("clk", Pins("H17")),
 106         Subsignal("data0_n", Pins("H16")),
 107         Subsignal("data1", Pins("F17")),
 108         Subsignal("data2_n", Pins("F16")),
 109         Subsignal("scl", Pins("J16")),
 110         Subsignal("sda", Pins("K16")),
 111         IOStandard("LVCMOS33")
 112     ),
 113     ("dvi_pots", 0,
 114         Subsignal("charge", Pins("A18")),        # SD_DAT0
 115         Subsignal("blackout", Pins("C17")),        # SD_DAT2
 116         Subsignal("crossfade", Pins("A17")),    # SD_DAT3
 117         IOStandard("LVCMOS33")
 118     )
 119 ]
 120
 121
 122 class Platform(XilinxPlatform):
 123     identifier = 0x4D31
 124     default_clk_name = "clk50"
 125     default_clk_period = 20
 126
 127     def __init__(self):
 128         XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io)
 129
 130     def create_programmer(self):
 131         return UrJTAG(cable="milkymist", flash_proxy_basename="fjmem-m1.bit")
 132
 133     def do_finalize(self, fragment):
 134         XilinxPlatform.do_finalize(self, fragment)
 135
 136         try:
 137             eth_clocks = self.lookup_request("eth_clocks")
 138             self.add_period_constraint(eth_clocks.rx, 40)
 139             self.add_period_constraint(eth_clocks.tx, 40)
 140             self.add_platform_command("""
 141 TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns;
 142 TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns;
 143 """, phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx)
 144         except ConstraintError:
 145             pass
 146
 147         for i in range(2):
 148             si = "dviclk"+str(i)
 149             try:
 150                 self.add_period_constraint(self.lookup_request("dvi_in", i).clk, 26.7)
 151             except ConstraintError:
 152                 pass