litex/soc/cores/cpu/lm32/core.py

   1 import os
   2
   3 from litex.gen import *
   4
   5 from litex.soc.interconnect import wishbone
   6
   7
   8 class LM32(Module):
   9     def __init__(self, platform, eba_reset):
  10         self.ibus = i = wishbone.Interface()
  11         self.dbus = d = wishbone.Interface()
  12         self.interrupt = Signal(32)
  13
  14         ###
  15
  16         i_adr_o = Signal(32)
  17         d_adr_o = Signal(32)
  18         self.specials += Instance("lm32_cpu",
  19                                    p_eba_reset=Instance.PreformattedParam("32'h{:08x}".format(eba_reset)),
  20
  21                                    i_clk_i=ClockSignal(),
  22                                    i_rst_i=ResetSignal(),
  23
  24                                    i_interrupt=self.interrupt,
  25
  26                                    o_I_ADR_O=i_adr_o,
  27                                    o_I_DAT_O=i.dat_w,
  28                                    o_I_SEL_O=i.sel,
  29                                    o_I_CYC_O=i.cyc,
  30                                    o_I_STB_O=i.stb,
  31                                    o_I_WE_O=i.we,
  32                                    o_I_CTI_O=i.cti,
  33                                    o_I_BTE_O=i.bte,
  34                                    i_I_DAT_I=i.dat_r,
  35                                    i_I_ACK_I=i.ack,
  36                                    i_I_ERR_I=i.err,
  37                                    i_I_RTY_I=0,
  38
  39                                    o_D_ADR_O=d_adr_o,
  40                                    o_D_DAT_O=d.dat_w,
  41                                    o_D_SEL_O=d.sel,
  42                                    o_D_CYC_O=d.cyc,
  43                                    o_D_STB_O=d.stb,
  44                                    o_D_WE_O=d.we,
  45                                    o_D_CTI_O=d.cti,
  46                                    o_D_BTE_O=d.bte,
  47                                    i_D_DAT_I=d.dat_r,
  48                                    i_D_ACK_I=d.ack,
  49                                    i_D_ERR_I=d.err,
  50                                    i_D_RTY_I=0)
  51
  52         self.comb += [
  53             self.ibus.adr.eq(i_adr_o[2:]),
  54             self.dbus.adr.eq(d_adr_o[2:])
  55         ]
  56
  57         # add Verilog sources
  58         vdir = os.path.join(
  59             os.path.abspath(os.path.dirname(__file__)), "verilog")
  60         platform.add_sources(os.path.join(vdir, "submodule", "rtl"),
  61                 "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
  62                 "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
  63                 "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
  64                 "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
  65                 "lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
  66         platform.add_verilog_include_path(vdir)