litex/soc/cores/cpu/lm32/verilog/lm32_config.v

   1 `ifdef LM32_CONFIG_V
   2 `else
   3 `define LM32_CONFIG_V
   4
   5 //
   6 // EXCEPTION VECTORS BASE ADDRESS
   7 //
   8
   9 // Base address for exception vectors
  10 `define CFG_EBA_RESET 32'h00000000
  11
  12 // Base address for the debug exception vectors. If the DC_RE flag is
  13 // set or the at_debug signal is asserted (see CFG_ALTERNATE_EBA) this
  14 // will also be used for normal exception vectors.
  15 `define CFG_DEBA_RESET 32'h10000000
  16
  17 // Enable exception vector remapping by external signal
  18 //`define CFG_ALTERNATE_EBA
  19
  20
  21 //
  22 // ALU OPTIONS
  23 //
  24
  25 // Enable sign-extension instructions
  26 `define CFG_SIGN_EXTEND_ENABLED
  27
  28 // Shifter
  29 // You may either enable the piplined or the multi-cycle barrel
  30 // shifter. The multi-cycle shifter will stall the pipeline until
  31 // the result is available after 32 cycles.
  32 // If both options are disabled, only "right shift by one bit" is
  33 // available.
  34 //`define CFG_MC_BARREL_SHIFT_ENABLED
  35 `define CFG_PL_BARREL_SHIFT_ENABLED
  36
  37 // Multiplier
  38 // The multiplier is available either in a multi-cycle version or
  39 // in a pipelined one. The multi-cycle multiplier stalls the pipe
  40 // for 32 cycles. If both options are disabled, multiply operations
  41 // are not supported.
  42 //`define CFG_MC_MULTIPLY_ENABLED
  43 `define CFG_PL_MULTIPLY_ENABLED
  44
  45 // Enable the multi-cycle divider. Stalls the pipe until the result
  46 // is ready after 32 cycles. If disabled, the divide operation is not
  47 // supported.
  48 `define CFG_MC_DIVIDE_ENABLED
  49
  50
  51 //
  52 // INTERRUPTS
  53 //
  54
  55 // Enable support for 32 hardware interrupts
  56 `define CFG_INTERRUPTS_ENABLED
  57
  58 // Enable level-sensitive interrupts. The interrupt line status is
  59 // reflected in the IP register, which is then read-only.
  60 `define CFG_LEVEL_SENSITIVE_INTERRUPTS
  61
  62
  63 //
  64 // USER INSTRUCTION
  65 //
  66
  67 // Enable support for the user opcode.
  68 //`define CFG_USER_ENABLED
  69
  70
  71 //
  72 // MEMORY MANAGEMENT UNIT
  73 //
  74
  75 // Enable instruction and data translation lookaside buffers and
  76 // restricted user mode.
  77 //`define CFG_MMU_ENABLED
  78
  79
  80 //
  81 // CACHE
  82 //
  83
  84 // Instruction cache
  85 `define CFG_ICACHE_ENABLED
  86 `define CFG_ICACHE_ASSOCIATIVITY   1
  87 `define CFG_ICACHE_SETS            256
  88 `define CFG_ICACHE_BYTES_PER_LINE  16
  89 `define CFG_ICACHE_BASE_ADDRESS    32'h00000000
  90 `define CFG_ICACHE_LIMIT           32'h7fffffff
  91
  92 // Data cache
  93 `define CFG_DCACHE_ENABLED
  94 `define CFG_DCACHE_ASSOCIATIVITY   1
  95 `define CFG_DCACHE_SETS            256
  96 `define CFG_DCACHE_BYTES_PER_LINE  16
  97 `define CFG_DCACHE_BASE_ADDRESS    32'h00000000
  98 `define CFG_DCACHE_LIMIT           32'h7fffffff
  99
 100
 101 //
 102 // DEBUG OPTION
 103 //
 104
 105 // Globally enable debugging
 106 //`define CFG_DEBUG_ENABLED
 107
 108 // Enable the hardware JTAG debugging interface.
 109 // Note: to use this, there must be a special JTAG module for your
 110 //       device. At the moment, there is only support for the
 111 //       Spartan-6.
 112 //`define CFG_JTAG_ENABLED
 113
 114 // JTAG UART is a communication channel which uses JTAG to transmit
 115 // and receive bytes to and from the host computer.
 116 //`define CFG_JTAG_UART_ENABLED
 117
 118 // Enable reading and writing to the memory and writing CSRs using
 119 // the JTAG interface.
 120 //`define CFG_HW_DEBUG_ENABLED
 121
 122 // Number of hardware watchpoints, max. 4
 123 //`define CFG_WATCHPOINTS 32'h4
 124
 125 // Enable hardware breakpoints
 126 //`define CFG_ROM_DEBUG_ENABLED
 127
 128 // Number of hardware breakpoints, max. 4
 129 //`define CFG_BREAKPOINTS 32'h4
 130
 131 // Put the processor into debug mode by an external signal. That is,
 132 // raise a breakpoint exception. This is useful if you have a debug
 133 // monitor and a serial line and you want to trap into the monitor on a
 134 // BREAK symbol on the serial line.
 135 //`define CFG_EXTERNAL_BREAK_ENABLED
 136
 137
 138 //
 139 // REGISTER FILE
 140 //
 141
 142 // The following option explicitly infers block RAM for the register
 143 // file. There is extra logic to avoid parallel writes and reads.
 144 // Normally, if your synthesizer is smart enough, this should not be
 145 // necessary because it will automatically infer block RAM for you.
 146 //`define CFG_EBR_POSEDGE_REGISTER_FILE
 147
 148 // Explicitly infers block RAM, too. But it uses two different clocks,
 149 // one being shifted by 180deg, for the read and write port. Therefore,
 150 // no additional logic to avoid the parallel write/reads.
 151 //`define CFG_EBR_NEGEDGE_REGISTER_FILE
 152
 153
 154 //
 155 // MISCELLANEOUS
 156 //
 157
 158 // Exceptions on wishbone bus errors
 159 //`define CFG_BUS_ERRORS_ENABLED
 160
 161 // Enable the cycle counter
 162 `define CFG_CYCLE_COUNTER_ENABLED
 163
 164 // Embedded instruction ROM using on-chip block RAM
 165 //`define CFG_IROM_ENABLED
 166 //`define CFG_IROM_INIT_FILE     "NONE"
 167 //`define CFG_IROM_BASE_ADDRESS  32'h10000000
 168 //`define CFG_IROM_LIMIT         32'h10000fff
 169
 170 // Embedded data RAM using on-chip block RAM
 171 //`define CFG_DRAM_ENABLED
 172 //`define CFG_DRAM_INIT_FILE     "NONE"
 173 //`define CFG_DRAM_BASE_ADDRESS  32'h20000000
 174 //`define CFG_DRAM_LIMIT         32'h20000fff
 175
 176 // Trace unit
 177 //`define CFG_TRACE_ENABLED
 178
 179 // Resolve unconditional branches already in the X stage (UNTESTED!)
 180 //`define CFG_FAST_UNCONDITIONAL_BRANCH
 181
 182 // log2 function
 183 // If your simulator/synthesizer does not support the $clog2 system
 184 // function you can use a constant function instead.
 185
 186 function integer clog2;
 187   input integer value;
 188   begin
 189     value = value - 1;
 190     for (clog2 = 0; value > 0; clog2 = clog2 + 1)
 191       value = value >> 1;
 192   end
 193 endfunction
 194
 195 `define CLOG2 clog2
 196
 197 //`define CLOG2 $clog2
 198
 199 `endif