litex/soc/cores/cpu/microwatt/core.py

   1 # This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
   2 # This file is Copyright (c) 2019 Benjamin Herrenschmidt <benh@ozlabs.org>
   3 # License: BSD
   4
   5 import os
   6
   7 from migen import *
   8
   9 from litex import get_data_mod
  10 from litex.soc.interconnect import wishbone
  11 from litex.soc.cores.cpu import CPU
  12
  13
  14 CPU_VARIANTS = ["standard"]
  15
  16
  17 class Microwatt(CPU):
  18     name                 = "microwatt"
  19     human_name           = "Microwatt"
  20     data_width           = 64
  21     endianness           = "little"
  22     gcc_triple           = ("powerpc64le-linux")
  23     linker_output_format = "elf64-powerpcle"
  24     io_regions           = {0xc0000000: 0x10000000} # origin, length
  25
  26     @property
  27     def mem_map(self):
  28         return {"csr": 0xc0000000}
  29
  30     @property
  31     def gcc_flags(self):
  32         flags  = "-m64 "
  33         flags += "-mabi=elfv2 "
  34         flags += "-msoft-float "
  35         flags += "-mno-string "
  36         flags += "-mno-multiple "
  37         flags += "-mno-vsx "
  38         flags += "-mno-altivec "
  39         flags += "-mlittle-endian "
  40         flags += "-mstrict-align "
  41         flags += "-D__microwatt__ "
  42         return flags
  43
  44     def __init__(self, platform, variant="standard"):
  45         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
  46         self.platform     = platform
  47         self.variant      = variant
  48         self.reset        = Signal()
  49         self.wb_insn      = wb_insn = wishbone.Interface(data_width=64, adr_width=28)
  50         self.wb_data      = wb_data = wishbone.Interface(data_width=64, adr_width=28)
  51         self.periph_buses = [wb_insn, wb_data]
  52         self.memory_buses = []
  53
  54         # # #
  55
  56         self.cpu_params = dict(
  57             # Clock / Reset
  58             i_clk                 = ClockSignal(),
  59             i_rst                 = ResetSignal() | self.reset,
  60
  61             # Wishbone instruction bus
  62             i_wishbone_insn_dat_r = wb_insn.dat_r,
  63             i_wishbone_insn_ack   = wb_insn.ack,
  64             i_wishbone_insn_stall = wb_insn.cyc & ~wb_insn.ack, # No burst support
  65
  66             o_wishbone_insn_adr   = Cat(Signal(4), wb_insn.adr),
  67             o_wishbone_insn_dat_w = wb_insn.dat_w,
  68             o_wishbone_insn_cyc   = wb_insn.cyc,
  69             o_wishbone_insn_stb   = wb_insn.stb,
  70             o_wishbone_insn_sel   = wb_insn.sel,
  71             o_wishbone_insn_we    = wb_insn.we,
  72
  73             # Wishbone data bus
  74             i_wishbone_data_dat_r = wb_data.dat_r,
  75             i_wishbone_data_ack   = wb_data.ack,
  76             i_wishbone_data_stall = wb_data.cyc & ~wb_data.ack, # No burst support
  77
  78             o_wishbone_data_adr   = Cat(Signal(4), wb_data.adr),
  79             o_wishbone_data_dat_w = wb_data.dat_w,
  80             o_wishbone_data_cyc   = wb_data.cyc,
  81             o_wishbone_data_stb   = wb_data.stb,
  82             o_wishbone_data_sel   = wb_data.sel,
  83             o_wishbone_data_we    = wb_data.we,
  84
  85             # Debug bus
  86             i_dmi_addr            = 0,
  87             i_dmi_din             = 0,
  88             #o_dmi_dout           =,
  89             i_dmi_req             = 0,
  90             i_dmi_wr              = 0,
  91             #o_dmi_ack            =,
  92         )
  93
  94         # add vhdl sources
  95         self.add_sources(platform)
  96
  97     def set_reset_address(self, reset_address):
  98         assert not hasattr(self, "reset_address")
  99         self.reset_address = reset_address
 100         assert reset_address == 0x00000000
 101
 102     @staticmethod
 103     def add_sources(platform):
 104         sdir = os.path.join(
 105             get_data_mod("cpu", "microwatt").data_location,
 106             "sources")
 107         platform.add_sources(sdir,
 108             # Common / Types / Helpers
 109             "decode_types.vhdl",
 110             "wishbone_types.vhdl",
 111             "utils.vhdl",
 112             "common.vhdl",
 113             "helpers.vhdl",
 114
 115             # Fetch
 116             "fetch1.vhdl",
 117             "fetch2.vhdl",
 118
 119             # Instruction/Data Cache
 120             "cache_ram.vhdl",
 121             "plru.vhdl",
 122             "dcache.vhdl",
 123             "icache.vhdl",
 124
 125             # Decode
 126             "insn_helpers.vhdl",
 127             "decode1.vhdl",
 128             "gpr_hazard.vhdl",
 129             "cr_hazard.vhdl",
 130             "control.vhdl",
 131             "decode2.vhdl",
 132
 133             # Register/CR File
 134             "register_file.vhdl",
 135             "crhelpers.vhdl",
 136             "cr_file.vhdl",
 137
 138             # Execute
 139             "ppc_fx_insns.vhdl",
 140             "logical.vhdl",
 141             "rotator.vhdl",
 142             "countzero.vhdl",
 143             "execute1.vhdl",
 144
 145             # Load/Store
 146             "loadstore1.vhdl",
 147
 148             # Multiply/Divide
 149             "multiply.vhdl",
 150             "divider.vhdl",
 151
 152             # Writeback
 153             "writeback.vhdl",
 154
 155             # Core
 156             "core_debug.vhdl",
 157             "core.vhdl",
 158         )
 159         platform.add_source(os.path.join(sdir, "..", "microwatt_wrapper.vhdl"))
 160
 161     def do_finalize(self):
 162         self.specials += Instance("microwatt_wrapper", **self.cpu_params)