soc: add use_loc_if_exists on SoCCSR.add to use current location is already defined
[litex.git] / litex / soc / integration / soc.py
1 #!/usr/bin/env python3
2
3 # This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
4 # License: BSD
5
6 import logging
7 import time
8 import datetime
9
10 from migen import *
11
12 from litex.soc.interconnect import wishbone
13
14 # TODO:
15 # - replace raise with exit on logging error.
16 # - use common module for SoCCSR/SoCIRQ.
17 # - add configurable CSR paging.
18 # - manage IO/Linker regions.
19
20 logging.basicConfig(level=logging.INFO)
21
22 # Helpers ------------------------------------------------------------------------------------------
23 def colorer(s, color="bright"):
24 header = {
25 "bright": "\x1b[1m",
26 "green": "\x1b[32m",
27 "cyan": "\x1b[36m",
28 "red": "\x1b[31m",
29 "yellow": "\x1b[33m",
30 "underline": "\x1b[4m"}[color]
31 trailer = "\x1b[0m"
32 return header + str(s) + trailer
33
34 def buildtime(with_time=True):
35 fmt = "%Y-%m-%d %H:%M:%S" if with_time else "%Y-%m-%d"
36 return datetime.datetime.fromtimestamp(time.time()).strftime("%Y-%m-%d %H:%M:%S")
37
38 # SoCRegion ----------------------------------------------------------------------------------------
39
40 class SoCRegion:
41 def __init__(self, origin=None, size=None, cached=True):
42 self.logger = logging.getLogger("SoCRegion")
43 self.origin = origin
44 self.size = size
45 self.cached = cached
46
47 def decoder(self):
48 origin = self.origin
49 size = self.size
50 origin &= ~0x80000000
51 size = 2**log2_int(size, False)
52 if (origin & (size - 1)) != 0:
53 self.logger.error("Origin needs to be aligned on size:")
54 self.logger.error(self)
55 raise
56 origin >>= 2 # bytes to words aligned
57 size >>= 2 # bytes to words aligned
58 return lambda a: (a[log2_int(size):-1] == (origin >> log2_int(size)))
59
60 def __str__(self):
61 r = ""
62 if self.origin is not None:
63 r += "Origin: {}, ".format(colorer("0x{:08x}".format(self.origin)))
64 if self.size is not None:
65 r += "Size: {}, ".format(colorer("0x{:08x}".format(self.size)))
66 r += "Cached: {}".format(colorer(self.cached))
67 return r
68
69
70 class SoCLinkerRegion(SoCRegion):
71 pass
72
73 # SoCBus -------------------------------------------------------------------------------------------
74
75 class SoCBus:
76 supported_standard = ["wishbone"]
77 supported_data_width = [32, 64]
78 supported_address_width = [32]
79
80 # Creation -------------------------------------------------------------------------------------
81 def __init__(self, standard, data_width=32, address_width=32, timeout=1e6, reserved_regions={}):
82 self.logger = logging.getLogger("SoCBus")
83 self.logger.info(colorer("Creating new Bus Handler...", color="cyan"))
84
85 # Check Standard
86 if standard not in self.supported_standard:
87 self.logger.error("Unsupported Standard: {} supporteds: {:s}".format(
88 colorer(standard, color="red"),
89 colorer(", ".join(self.supported_standard), color="green")))
90 raise
91
92 # Check Data Width
93 if data_width not in self.supported_data_width:
94 self.logger.error("Unsupported Data_Width: {} supporteds: {:s}".format(
95 colorer(data_width, color="red"),
96 colorer(", ".join(str(x) for x in self.supported_data_width), color="green")))
97 raise
98
99 # Check Address Width
100 if address_width not in self.supported_address_width:
101 self.logger.error("Unsupported Address Width: {} supporteds: {:s}".format(
102 colorer(data_width, color="red"),
103 colorer(", ".join(str(x) for x in self.supported_address_width), color="green")))
104 raise
105
106 # Create Bus
107 self.standard = standard
108 self.data_width = data_width
109 self.address_width = address_width
110 self.masters = {}
111 self.slaves = {}
112 self.regions = {}
113 self.timeout = timeout
114 self.logger.info("{}-bit {} Bus, {}GiB Address Space.".format(
115 colorer(data_width), colorer(standard), colorer(2**address_width/2**30)))
116
117 # Adding reserved regions
118 self.logger.info("Adding {} Regions...".format(colorer("reserved")))
119 for name, region in reserved_regions.items():
120 if isinstance(region, int):
121 region = SoCRegion(origin=region, size=0x1000000)
122 self.add_region(name, region)
123
124 self.logger.info(colorer("Bus Handler created.", color="cyan"))
125
126 # Add/Allog/Check Regions ----------------------------------------------------------------------
127 def add_region(self, name, region):
128 allocated = False
129 # Check if SoCLinkerRegion
130 if isinstance(region, SoCLinkerRegion):
131 self.logger.info("FIXME: SoCLinkerRegion")
132 # Check if SoCRegion
133 elif isinstance(region, SoCRegion):
134 # If no origin specified, allocate region.
135 if region.origin is None:
136 allocated = True
137 region = self.alloc_region(region.size, region.cached)
138 self.regions[name] = region
139 # Else add region and check for overlaps.
140 else:
141 self.regions[name] = region
142 overlap = self.check_region(self.regions)
143 if overlap is not None:
144 self.logger.error("Region overlap between {} and {}:".format(
145 colorer(overlap[0], color="red"),
146 colorer(overlap[1], color="red")))
147 self.logger.error(str(self.regions[overlap[0]]))
148 self.logger.error(str(self.regions[overlap[1]]))
149 raise
150 self.logger.info("{} Region {} {}.".format(
151 colorer(name, color="underline"),
152 colorer("allocated" if allocated else "added", color="yellow" if allocated else "green"),
153 str(region)))
154 else:
155 self.logger.error("{} is not a supported Region".format(colorer(name, color="red")))
156 raise
157
158 def alloc_region(self, size, cached=True):
159 self.logger.info("Allocating {} Region of size {}...".format(
160 colorer("Cached" if cached else "IO"),
161 colorer("0x{:08x}".format(size))))
162
163 # Limit Search Regions
164 uncached_regions = {}
165 for _, region in self.regions.items():
166 if region.cached == False:
167 uncached_regions[name] = region
168 if cached == False:
169 search_regions = uncached_regions
170 else:
171 search_regions = {"main": SoCRegion(origin=0x00000000, size=2**self.address_width-1)}
172
173 # Iterate on Search_Regions to find a Candidate
174 for _, search_region in search_regions.items():
175 origin = search_region.origin
176 while (origin + size) < (search_region.origin + search_region.size):
177 # Create a Candicate.
178 candidate = SoCRegion(origin=origin, size=size, cached=cached)
179 overlap = False
180 # Check Candidate does not overlap with allocated existing regions
181 for _, allocated in self.regions.items():
182 if self.check_region({"0": allocated, "1": candidate}) is not None:
183 origin = allocated.origin + allocated.size
184 overlap = True
185 break
186 if not overlap:
187 # If no overlap, the Candidate is selected
188 return candidate
189
190 self.logger.error("Not enough Address Space to allocate Region")
191 raise
192
193 def check_region(self, regions):
194 i = 0
195 while i < len(regions):
196 n0 = list(regions.keys())[i]
197 r0 = regions[n0]
198 for n1 in list(regions.keys())[i+1:]:
199 r1 = regions[n1]
200 if isinstance(r0, SoCLinkerRegion) or isinstance(r1, SoCLinkerRegion):
201 continue
202 if r0.origin >= (r1.origin + r1.size):
203 continue
204 if r1.origin >= (r0.origin + r0.size):
205 continue
206 return (n0, n1)
207 i += 1
208 return None
209
210 # Add Master/Slave -----------------------------------------------------------------------------
211 def add_master(self, name=None, master=None, io_regions={}):
212 if name is None:
213 name = "master{:d}".format(len(self.masters))
214 if name in self.masters.keys():
215 self.logger.error("{} already declared as Bus Master:".format(colorer(name, color="red")))
216 self.logger.error(self)
217 raise
218 self.masters[name] = master
219 self.logger.info("{} {} as Bus Master.".format(colorer(name, color="underline"), colorer("added", color="green")))
220 # FIXME: handle IO regions
221
222 def add_slave(self, name=None, slave=None, region=None):
223 no_name = name is None
224 no_region = region is None
225 if no_name and no_region:
226 self.logger.error("Please specify at least {} or {} of Bus Slave".format(
227 colorer("name", color="red"),
228 colorer("region", color="red")))
229 raise
230 if no_name:
231 name = "slave{:d}".format(len(self.slaves))
232 if no_region:
233 region = self.regions.get(name, None)
234 if region is None:
235 self.logger.error("Unable to find Region {}".format(colorer(name, color="red")))
236 raise
237 else:
238 self.add_region(name, region)
239 if name in self.slaves.keys():
240 self.logger.error("{} already declared as Bus Slave:".format(colorer(name, color="red")))
241 self.logger.error(self)
242 raise
243 self.slaves[name] = slave
244 self.logger.info("{} {} as Bus Slave.".format(
245 colorer(name, color="underline"),
246 colorer("added", color="green")))
247
248 # Str ------------------------------------------------------------------------------------------
249 def __str__(self):
250 r = "{}-bit {} Bus, {}GiB Address Space.\n".format(
251 colorer(self.data_width), colorer(self.standard), colorer(2**self.address_width/2**30))
252 r += "Bus Regions: ({})\n".format(len(self.regions.keys())) if len(self.regions.keys()) else ""
253 for name, region in self.regions.items():
254 r += colorer(name, color="underline") + " "*(20-len(name)) + ": " + str(region) + "\n"
255 r += "Bus Masters: ({})\n".format(len(self.masters.keys())) if len(self.masters.keys()) else ""
256 for name in self.masters.keys():
257 r += "- {}\n".format(colorer(name, color="underline"))
258 r += "Bus Slaves: ({})\n".format(len(self.slaves.keys())) if len(self.slaves.keys()) else ""
259 for name in self.slaves.keys():
260 r += "- {}\n".format(colorer(name, color="underline"))
261 r = r[:-1]
262 return r
263
264 # SoCCSR ----------------------------------------------------------------------------------------
265
266 class SoCCSR:
267 supported_data_width = [8, 32]
268 supported_address_width = [14, 15]
269 supported_alignment = [32, 64]
270 supported_paging = [0x800]
271
272 # Creation -------------------------------------------------------------------------------------
273 def __init__(self, data_width=32, address_width=14, alignment=32, paging=0x800, reserved_csrs={}):
274 self.logger = logging.getLogger("SoCCSR")
275 self.logger.info(colorer("Creating new CSR Handler...", color="cyan"))
276
277 # Check Data Width
278 if data_width not in self.supported_data_width:
279 self.logger.error("Unsupported data_width: {} supporteds: {:s}".format(
280 colorer(data_width, color="red"),
281 colorer(", ".join(str(x) for x in self.supported_data_width)), color="green"))
282 raise
283
284 # Check Address Width
285 if address_width not in self.supported_address_width:
286 self.logger.error("Unsupported address_width: {} supporteds: {:s}".format(
287 colorer(address_width, color="red"),
288 colorer(", ".join(str(x) for x in self.supported_address_width), color="green")))
289 raise
290
291 # Check Alignment
292 if alignment not in self.supported_alignment:
293 self.logger.error("Unsupported alignment: {} supporteds: {:s}".format(
294 colorer(alignment, color="red"),
295 colorer(", ".join(str(x) for x in self.supported_alignment), color="green")))
296 raise
297
298 # Check Paging
299 if paging not in self.supported_paging:
300 self.logger.error("Unsupported paging: {} supporteds: {:s}".format(
301 colorer(paging, color="red"),
302 colorer(", ".join(str(x) for x in self.supported_paging), color="green")))
303 raise
304
305 # Create CSR Handler
306 self.data_width = data_width
307 self.address_width = address_width
308 self.alignment = alignment
309 self.paging = paging
310 self.csrs = {}
311 self.n_csrs = 4*2**address_width//paging # FIXME
312 self.logger.info("{}-bit CSR Bus, {}KiB Address Space, {}B Paging (Up to {} Locations).\n".format(
313 colorer(self.data_width),
314 colorer(2**self.address_width/2**10),
315 colorer(self.paging),
316 self.n_csrs))
317
318 # Adding reserved CSRs
319 self.logger.info("Adding {} CSRs...".format(colorer("reserved")))
320 for name, n in reserved_csrs.items():
321 self.add(name, n)
322
323 self.logger.info(colorer("CSR Bus Handler created.", color="cyan"))
324
325 # Add ------------------------------------------------------------------------------------------
326 def add(self, name, n=None, use_loc_if_exists=False):
327 allocated = False
328 if not (use_loc_if_exists and name in self.csrs.keys()):
329 if name in self.csrs.keys():
330 self.logger.error("{} CSR name already used.".format(colorer(name, "red")))
331 self.logger.error(self)
332 raise
333 if n in self.csrs.values():
334 self.logger.error("{} CSR Location already used.".format(colorer(n, "red")))
335 self.logger.error(self)
336 raise
337 if n is None:
338 allocated = True
339 n = self.alloc(name)
340 else:
341 if n < 0:
342 self.logger.error("{} CSR Location should be positive.".format(
343 colorer(n, color="red")))
344 raise
345 if n > self.n_csrs:
346 self.logger.error("{} CSR Location too high (Up to {}).".format(
347 colorer(n, color="red"),
348 colorer(self.n_csrs, color="green")))
349 raise
350 self.csrs[name] = n
351 else:
352 n = self.csrs[name]
353 self.logger.info("{} CSR {} at Location {}.".format(
354 colorer(name, color="underline"),
355 colorer("allocated" if allocated else "added", color="yellow" if allocated else "green"),
356 colorer(n)))
357
358 # Alloc ----------------------------------------------------------------------------------------
359 def alloc(self, name):
360 for n in range(self.data_width//8*2**self.address_width//self.paging):
361 if n not in self.csrs.values():
362 return n
363 self.logger.error("Not enough CSR Locations.")
364 self.logger.error(self)
365 raise
366
367 # Str ------------------------------------------------------------------------------------------
368 def __str__(self):
369 r = "{}-bit CSR Bus, {}KiB Address Space, {}B Paging (Up to {} Locations).\n".format(
370 colorer(self.data_width),
371 colorer(2**self.address_width/2**10),
372 colorer(self.paging),
373 self.n_csrs)
374 r += "CSR Locations: ({})\n".format(len(self.csrs.keys())) if len(self.csrs.keys()) else ""
375 for name in self.csrs.keys():
376 r += "- {}{}: {}\n".format(colorer(name, color="underline"), " "*(20-len(name)), colorer(self.csrs[name]))
377 r = r[:-1]
378 return r
379
380 # SoCIRQ -------------------------------------------------------------------------------------------
381
382 class SoCIRQ:
383 # Creation -------------------------------------------------------------------------------------
384 def __init__(self, n_irqs=32, reserved_irqs={}):
385 self.logger = logging.getLogger("SoCIRQ")
386 self.logger.info(colorer("Creating new SoC IRQ Handler...", color="cyan"))
387
388 # Check IRQ Number
389 if n_irqs > 32:
390 self.logger.error("Unsupported IRQs number: {} supporteds: {:s}".format(
391 colorer(n, color="red"), colorer("Up to 32", color="green")))
392 raise
393
394 # Create IRQ Handler
395 self.n_irqs = n_irqs
396 self.irqs = {}
397 self.logger.info("IRQ Handler (up to {} Locations).".format(colorer(n_irqs)))
398
399 # Adding reserved IRQs
400 self.logger.info("Adding {} IRQs...".format(colorer("reserved")))
401 for name, n in reserved_irqs.items():
402 self.add(name, n)
403
404 self.logger.info(colorer("IRQ Handler created.", color="cyan"))
405
406 # Add ------------------------------------------------------------------------------------------
407 def add(self, name, n=None):
408 allocated = False
409 if name in self.irqs.keys():
410 self.logger.error("{} IRQ name already used.".format(colorer(name, "red")))
411 self.logger.error(self)
412 raise
413 if n in self.irqs.values():
414 self.logger.error("{} IRQ Location already used.".format(colorer(n, "red")))
415 self.logger.error(self)
416 raise
417 if n is None:
418 allocated = True
419 n = self.alloc(name)
420 else:
421 if n < 0:
422 self.logger.error("{} IRQ Location should be positive.".format(
423 colorer(n, color="red")))
424 raise
425 if n > self.n_irqs:
426 self.logger.error("{} IRQ Location too high (Up to {}).".format(
427 colorer(n, color="red"),
428 colorer(self.n_csrs, color="green")))
429 raise
430 self.irqs[name] = n
431 self.logger.info("{} IRQ {} at Location {}.".format(
432 colorer(name, color="underline"),
433 colorer("allocated" if allocated else "added", color="yellow" if allocated else "green"),
434 colorer(n)))
435
436 # Alloc ----------------------------------------------------------------------------------------
437 def alloc(self, name):
438 for n in range(self.n_irqs):
439 if n not in self.irqs.values():
440 return n
441 self.logger.error("Not enough Locations.")
442 self.logger.error(self)
443 raise
444
445 # Str ------------------------------------------------------------------------------------------
446 def __str__(self):
447 r ="IRQ Handler (up to {} Locations).\n".format(colorer(self.n_irqs))
448 r += "IRQs Locations:\n" if len(self.irqs.keys()) else ""
449 for name in self.irqs.keys():
450 r += "- {}{}: {}\n".format(colorer(name, color="underline"), " "*(20-len(name)), colorer(self.irqs[name]))
451 r = r[:-1]
452 return r
453
454 # SoC ----------------------------------------------------------------------------------------------
455
456 class SoC(Module):
457 def __init__(self,
458 bus_standard = "wishbone",
459 bus_data_width = 32,
460 bus_address_width = 32,
461 bus_timeout = 1e6,
462 bus_reserved_regions = {},
463
464 csr_data_width = 32,
465 csr_address_width = 14,
466 csr_alignment = 32,
467 csr_paging = 0x800,
468 csr_reserved_csrs = {},
469
470 irq_n_irqs = 32,
471 irq_reserved_irqs = {},
472 ):
473
474 self.logger = logging.getLogger("SoC")
475 self.logger.info(colorer(" __ _ __ _ __ ", color="bright"))
476 self.logger.info(colorer(" / / (_) /____ | |/_/ ", color="bright"))
477 self.logger.info(colorer(" / /__/ / __/ -_)> < ", color="bright"))
478 self.logger.info(colorer(" /____/_/\\__/\\__/_/|_| ", color="bright"))
479 self.logger.info(colorer(" Build your hardware, easily!", color="bright"))
480
481 self.logger.info(colorer("-"*80, color="bright"))
482 self.logger.info(colorer("Creating new SoC... ({})".format(buildtime()), color="cyan"))
483 self.logger.info(colorer("-"*80, color="bright"))
484
485 # SoC Bus Handler --------------------------------------------------------------------------
486 self.bus = SoCBus(
487 standard = bus_standard,
488 data_width = bus_data_width,
489 address_width = bus_address_width,
490 timeout = bus_timeout,
491 reserved_regions = bus_reserved_regions,
492 )
493
494 # SoC Bus Handler --------------------------------------------------------------------------
495 self.csr = SoCCSR(
496 data_width = csr_data_width,
497 address_width = csr_address_width,
498 alignment = csr_alignment,
499 paging = csr_paging,
500 reserved_csrs = csr_reserved_csrs,
501 )
502
503 # SoC IRQ Handler --------------------------------------------------------------------------
504 self.irq = SoCIRQ(
505 n_irqs = irq_n_irqs,
506 reserved_irqs = irq_reserved_irqs
507 )
508
509 self.logger.info(colorer("-"*80, color="bright"))
510 self.logger.info(colorer("Initial SoC:", color="cyan"))
511 self.logger.info(colorer("-"*80, color="bright"))
512 self.logger.info(self.bus)
513 self.logger.info(self.csr)
514 self.logger.info(self.irq)
515 self.logger.info(colorer("-"*80, color="bright"))
516
517
518 def do_finalize(self):
519 self.logger.info(colorer("-"*80, color="bright"))
520 self.logger.info(colorer("Finalized SoC:", color="cyan"))
521 self.logger.info(colorer("-"*80, color="bright"))
522 self.logger.info(self.bus)
523 self.logger.info(self.csr)
524 self.logger.info(self.irq)
525 self.logger.info(colorer("-"*80, color="bright"))
526
527 # SoC Bus Interconnect ---------------------------------------------------------------------
528 bus_masters = self.bus.masters.values()
529 bus_slaves = [(self.bus.regions[n].decoder(), s) for n, s in self.bus.slaves.items()]
530 if len(bus_masters) and len(bus_slaves):
531 self.submodules.bus_interconnect = wishbone.InterconnectShared(
532 masters = bus_masters,
533 slaves = bus_slaves,
534 register = True,
535 timeout_cycles = self.bus.timeout)
536
537 #exit()
538
539 # Test (FIXME: move to litex/text and improve) -----------------------------------------------------
540
541 if __name__ == "__main__":
542 bus = SoCBus("wishbone", reserved_regions={
543 "rom": SoCRegion(origin=0x00000100, size=1024),
544 "ram": SoCRegion(size=512),
545 }
546 )
547 bus.add_master("cpu", None)
548 bus.add_slave("rom", None, SoCRegion(size=1024))
549 bus.add_slave("ram", None, SoCRegion(size=1024))
550
551
552 csr = SoCCSR(reserved_csrs={"ctrl": 0, "uart": 1})
553 csr.add("csr0")
554 csr.add("csr1", 0)
555 #csr.add("csr2", 46)
556 csr.add("csr3", -1)
557 print(bus)
558 print(csr)
559
560 irq = SoCIRQ(reserved_irqs={"uart": 1})
561
562 soc = SoC()