soc: move SoCController from soc_core to soc
[litex.git] / litex / soc / integration / soc.py
1 #!/usr/bin/env python3
2
3 # This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
4 # License: BSD
5
6 import logging
7 import time
8 import datetime
9
10 from migen import *
11
12 from litex.soc.interconnect.csr import *
13 from litex.soc.interconnect import wishbone
14
15 # TODO:
16 # - replace raise with exit on logging error.
17 # - add configurable CSR paging.
18 # - manage IO/Linker regions.
19
20 logging.basicConfig(level=logging.INFO)
21
22 # Helpers ------------------------------------------------------------------------------------------
23 def colorer(s, color="bright"):
24 header = {
25 "bright": "\x1b[1m",
26 "green": "\x1b[32m",
27 "cyan": "\x1b[36m",
28 "red": "\x1b[31m",
29 "yellow": "\x1b[33m",
30 "underline": "\x1b[4m"}[color]
31 trailer = "\x1b[0m"
32 return header + str(s) + trailer
33
34 def buildtime(with_time=True):
35 fmt = "%Y-%m-%d %H:%M:%S" if with_time else "%Y-%m-%d"
36 return datetime.datetime.fromtimestamp(time.time()).strftime("%Y-%m-%d %H:%M:%S")
37
38 # SoCRegion ----------------------------------------------------------------------------------------
39
40 class SoCRegion:
41 def __init__(self, origin=None, size=None, cached=True):
42 self.logger = logging.getLogger("SoCRegion")
43 self.origin = origin
44 self.size = size
45 self.cached = cached
46
47 def decoder(self):
48 origin = self.origin
49 size = self.size
50 origin &= ~0x80000000
51 size = 2**log2_int(size, False)
52 if (origin & (size - 1)) != 0:
53 self.logger.error("Origin needs to be aligned on size:")
54 self.logger.error(self)
55 raise
56 origin >>= 2 # bytes to words aligned
57 size >>= 2 # bytes to words aligned
58 return lambda a: (a[log2_int(size):-1] == (origin >> log2_int(size)))
59
60 def __str__(self):
61 r = ""
62 if self.origin is not None:
63 r += "Origin: {}, ".format(colorer("0x{:08x}".format(self.origin)))
64 if self.size is not None:
65 r += "Size: {}, ".format(colorer("0x{:08x}".format(self.size)))
66 r += "Cached: {}".format(colorer(self.cached))
67 return r
68
69
70 class SoCLinkerRegion(SoCRegion):
71 pass
72
73 # SoCBusHandler ------------------------------------------------------------------------------------
74
75 class SoCBusHandler:
76 supported_standard = ["wishbone"]
77 supported_data_width = [32, 64]
78 supported_address_width = [32]
79
80 # Creation -------------------------------------------------------------------------------------
81 def __init__(self, standard, data_width=32, address_width=32, timeout=1e6, reserved_regions={}):
82 self.logger = logging.getLogger("SoCBusHandler")
83 self.logger.info(colorer("Creating new Bus Handler...", color="cyan"))
84
85 # Check Standard
86 if standard not in self.supported_standard:
87 self.logger.error("Unsupported Standard: {} supporteds: {:s}".format(
88 colorer(standard, color="red"),
89 colorer(", ".join(self.supported_standard), color="green")))
90 raise
91
92 # Check Data Width
93 if data_width not in self.supported_data_width:
94 self.logger.error("Unsupported Data_Width: {} supporteds: {:s}".format(
95 colorer(data_width, color="red"),
96 colorer(", ".join(str(x) for x in self.supported_data_width), color="green")))
97 raise
98
99 # Check Address Width
100 if address_width not in self.supported_address_width:
101 self.logger.error("Unsupported Address Width: {} supporteds: {:s}".format(
102 colorer(data_width, color="red"),
103 colorer(", ".join(str(x) for x in self.supported_address_width), color="green")))
104 raise
105
106 # Create Bus
107 self.standard = standard
108 self.data_width = data_width
109 self.address_width = address_width
110 self.masters = {}
111 self.slaves = {}
112 self.regions = {}
113 self.timeout = timeout
114 self.logger.info("{}-bit {} Bus, {}GiB Address Space.".format(
115 colorer(data_width), colorer(standard), colorer(2**address_width/2**30)))
116
117 # Adding reserved regions
118 self.logger.info("Adding {} Regions...".format(colorer("reserved")))
119 for name, region in reserved_regions.items():
120 if isinstance(region, int):
121 region = SoCRegion(origin=region, size=0x1000000)
122 self.add_region(name, region)
123
124 self.logger.info(colorer("Bus Handler created.", color="cyan"))
125
126 # Add/Allog/Check Regions ----------------------------------------------------------------------
127 def add_region(self, name, region):
128 allocated = False
129 # Check if SoCLinkerRegion
130 if isinstance(region, SoCLinkerRegion):
131 self.logger.info("FIXME: SoCLinkerRegion")
132 # Check if SoCRegion
133 elif isinstance(region, SoCRegion):
134 # If no origin specified, allocate region.
135 if region.origin is None:
136 allocated = True
137 region = self.alloc_region(region.size, region.cached)
138 self.regions[name] = region
139 # Else add region and check for overlaps.
140 else:
141 self.regions[name] = region
142 overlap = self.check_region(self.regions)
143 if overlap is not None:
144 self.logger.error("Region overlap between {} and {}:".format(
145 colorer(overlap[0], color="red"),
146 colorer(overlap[1], color="red")))
147 self.logger.error(str(self.regions[overlap[0]]))
148 self.logger.error(str(self.regions[overlap[1]]))
149 raise
150 self.logger.info("{} Region {} {}.".format(
151 colorer(name, color="underline"),
152 colorer("allocated" if allocated else "added", color="yellow" if allocated else "green"),
153 str(region)))
154 else:
155 self.logger.error("{} is not a supported Region".format(colorer(name, color="red")))
156 raise
157
158 def alloc_region(self, size, cached=True):
159 self.logger.info("Allocating {} Region of size {}...".format(
160 colorer("Cached" if cached else "IO"),
161 colorer("0x{:08x}".format(size))))
162
163 # Limit Search Regions
164 uncached_regions = {}
165 for _, region in self.regions.items():
166 if region.cached == False:
167 uncached_regions[name] = region
168 if cached == False:
169 search_regions = uncached_regions
170 else:
171 search_regions = {"main": SoCRegion(origin=0x00000000, size=2**self.address_width-1)}
172
173 # Iterate on Search_Regions to find a Candidate
174 for _, search_region in search_regions.items():
175 origin = search_region.origin
176 while (origin + size) < (search_region.origin + search_region.size):
177 # Create a Candicate.
178 candidate = SoCRegion(origin=origin, size=size, cached=cached)
179 overlap = False
180 # Check Candidate does not overlap with allocated existing regions
181 for _, allocated in self.regions.items():
182 if self.check_region({"0": allocated, "1": candidate}) is not None:
183 origin = allocated.origin + allocated.size
184 overlap = True
185 break
186 if not overlap:
187 # If no overlap, the Candidate is selected
188 return candidate
189
190 self.logger.error("Not enough Address Space to allocate Region")
191 raise
192
193 def check_region(self, regions):
194 i = 0
195 while i < len(regions):
196 n0 = list(regions.keys())[i]
197 r0 = regions[n0]
198 for n1 in list(regions.keys())[i+1:]:
199 r1 = regions[n1]
200 if isinstance(r0, SoCLinkerRegion) or isinstance(r1, SoCLinkerRegion):
201 continue
202 if r0.origin >= (r1.origin + r1.size):
203 continue
204 if r1.origin >= (r0.origin + r0.size):
205 continue
206 return (n0, n1)
207 i += 1
208 return None
209
210 # Add Master/Slave -----------------------------------------------------------------------------
211 def add_master(self, name=None, master=None, io_regions={}):
212 if name is None:
213 name = "master{:d}".format(len(self.masters))
214 if name in self.masters.keys():
215 self.logger.error("{} already declared as Bus Master:".format(colorer(name, color="red")))
216 self.logger.error(self)
217 raise
218 self.masters[name] = master
219 self.logger.info("{} {} as Bus Master.".format(colorer(name, color="underline"), colorer("added", color="green")))
220 # FIXME: handle IO regions
221
222 def add_slave(self, name=None, slave=None, region=None):
223 no_name = name is None
224 no_region = region is None
225 if no_name and no_region:
226 self.logger.error("Please specify at least {} or {} of Bus Slave".format(
227 colorer("name", color="red"),
228 colorer("region", color="red")))
229 raise
230 if no_name:
231 name = "slave{:d}".format(len(self.slaves))
232 if no_region:
233 region = self.regions.get(name, None)
234 if region is None:
235 self.logger.error("Unable to find Region {}".format(colorer(name, color="red")))
236 raise
237 else:
238 self.add_region(name, region)
239 if name in self.slaves.keys():
240 self.logger.error("{} already declared as Bus Slave:".format(colorer(name, color="red")))
241 self.logger.error(self)
242 raise
243 self.slaves[name] = slave
244 self.logger.info("{} {} as Bus Slave.".format(
245 colorer(name, color="underline"),
246 colorer("added", color="green")))
247
248 # Str ------------------------------------------------------------------------------------------
249 def __str__(self):
250 r = "{}-bit {} Bus, {}GiB Address Space.\n".format(
251 colorer(self.data_width), colorer(self.standard), colorer(2**self.address_width/2**30))
252 r += "Bus Regions: ({})\n".format(len(self.regions.keys())) if len(self.regions.keys()) else ""
253 for name, region in self.regions.items():
254 r += colorer(name, color="underline") + " "*(20-len(name)) + ": " + str(region) + "\n"
255 r += "Bus Masters: ({})\n".format(len(self.masters.keys())) if len(self.masters.keys()) else ""
256 for name in self.masters.keys():
257 r += "- {}\n".format(colorer(name, color="underline"))
258 r += "Bus Slaves: ({})\n".format(len(self.slaves.keys())) if len(self.slaves.keys()) else ""
259 for name in self.slaves.keys():
260 r += "- {}\n".format(colorer(name, color="underline"))
261 r = r[:-1]
262 return r
263
264 # SoCLocHandler --------------------------------------------------------------------------------------
265
266 class SoCLocHandler:
267 # Creation -------------------------------------------------------------------------------------
268 def __init__(self, name, n_locs):
269 self.name = name
270 self.locs = {}
271 self.n_locs = n_locs
272
273 # Add ------------------------------------------------------------------------------------------
274 def add(self, name, n=None, use_loc_if_exists=False):
275 allocated = False
276 if not (use_loc_if_exists and name in self.locs.keys()):
277 if name in self.locs.keys():
278 self.logger.error("{} {} name already used.".format(colorer(name, "red"), self.name))
279 self.logger.error(self)
280 raise
281 if n in self.locs.values():
282 self.logger.error("{} {} Location already used.".format(colorer(n, "red"), self.name))
283 self.logger.error(self)
284 raise
285 if n is None:
286 allocated = True
287 n = self.alloc(name)
288 else:
289 if n < 0:
290 self.logger.error("{} {} Location should be positive.".format(
291 colorer(n, color="red"),
292 self.name))
293 raise
294 if n > self.n_locs:
295 self.logger.error("{} {} Location too high (Up to {}).".format(
296 colorer(n, color="red"),
297 self.name,
298 colorer(self.n_csrs, color="green")))
299 raise
300 self.locs[name] = n
301 else:
302 n = self.locs[name]
303 self.logger.info("{} {} {} at Location {}.".format(
304 colorer(name, color="underline"),
305 self.name,
306 colorer("allocated" if allocated else "added", color="yellow" if allocated else "green"),
307 colorer(n)))
308
309 # Alloc ----------------------------------------------------------------------------------------
310 def alloc(self, name):
311 for n in range(self.n_locs):
312 if n not in self.locs.values():
313 return n
314 self.logger.error("Not enough Locations.")
315 self.logger.error(self)
316 raise
317
318 # Str ------------------------------------------------------------------------------------------
319 def __str__(self):
320 r = "{} Locations: ({})\n".format(self.name, len(self.locs.keys())) if len(self.locs.keys()) else ""
321 for name in self.locs.keys():
322 r += "- {}{}: {}\n".format(colorer(name, color="underline"), " "*(20-len(name)), colorer(self.locs[name]))
323 return r
324
325 # SoCCSRHandler ------------------------------------------------------------------------------------
326
327 class SoCCSRHandler(SoCLocHandler):
328 supported_data_width = [8, 32]
329 supported_address_width = [14, 15]
330 supported_alignment = [32, 64]
331 supported_paging = [0x800]
332
333 # Creation -------------------------------------------------------------------------------------
334 def __init__(self, data_width=32, address_width=14, alignment=32, paging=0x800, reserved_csrs={}):
335 SoCLocHandler.__init__(self, "CSR", n_locs=4*2**address_width//paging) # FIXME
336 self.logger = logging.getLogger("SoCCSRHandler")
337 self.logger.info(colorer("Creating new CSR Handler...", color="cyan"))
338
339 # Check Data Width
340 if data_width not in self.supported_data_width:
341 self.logger.error("Unsupported data_width: {} supporteds: {:s}".format(
342 colorer(data_width, color="red"),
343 colorer(", ".join(str(x) for x in self.supported_data_width)), color="green"))
344 raise
345
346 # Check Address Width
347 if address_width not in self.supported_address_width:
348 self.logger.error("Unsupported address_width: {} supporteds: {:s}".format(
349 colorer(address_width, color="red"),
350 colorer(", ".join(str(x) for x in self.supported_address_width), color="green")))
351 raise
352
353 # Check Alignment
354 if alignment not in self.supported_alignment:
355 self.logger.error("Unsupported alignment: {} supporteds: {:s}".format(
356 colorer(alignment, color="red"),
357 colorer(", ".join(str(x) for x in self.supported_alignment), color="green")))
358 raise
359
360 # Check Paging
361 if paging not in self.supported_paging:
362 self.logger.error("Unsupported paging: {} supporteds: {:s}".format(
363 colorer(paging, color="red"),
364 colorer(", ".join(str(x) for x in self.supported_paging), color="green")))
365 raise
366
367 # Create CSR Handler
368 self.data_width = data_width
369 self.address_width = address_width
370 self.alignment = alignment
371 self.paging = paging
372 self.logger.info("{}-bit CSR Bus, {}KiB Address Space, {}B Paging (Up to {} Locations).\n".format(
373 colorer(self.data_width),
374 colorer(2**self.address_width/2**10),
375 colorer(self.paging),
376 colorer(self.n_locs)))
377
378 # Adding reserved CSRs
379 self.logger.info("Adding {} CSRs...".format(colorer("reserved")))
380 for name, n in reserved_csrs.items():
381 self.add(name, n)
382
383 self.logger.info(colorer("CSR Bus Handler created.", color="cyan"))
384
385 # Str ------------------------------------------------------------------------------------------
386 def __str__(self):
387 r = "{}-bit CSR Bus, {}KiB Address Space, {}B Paging (Up to {} Locations).\n".format(
388 colorer(self.data_width),
389 colorer(2**self.address_width/2**10),
390 colorer(self.paging),
391 colorer(self.n_locs))
392 r += SoCLocHandler.__str__(self)
393 r = r[:-1]
394 return r
395
396 # SoCIRQHandler ------------------------------------------------------------------------------------
397
398 class SoCIRQHandler(SoCLocHandler):
399 # Creation -------------------------------------------------------------------------------------
400 def __init__(self, n_irqs=32, reserved_irqs={}):
401 SoCLocHandler.__init__(self, "IRQ", n_locs=n_irqs)
402 self.logger = logging.getLogger("SoCIRQHandler")
403 self.logger.info(colorer("Creating new SoC IRQ Handler...", color="cyan"))
404
405 # Check IRQ Number
406 if n_irqs > 32:
407 self.logger.error("Unsupported IRQs number: {} supporteds: {:s}".format(
408 colorer(n, color="red"), colorer("Up to 32", color="green")))
409 raise
410
411 # Create IRQ Handler
412 self.logger.info("IRQ Handler (up to {} Locations).".format(colorer(n_irqs)))
413
414 # Adding reserved IRQs
415 self.logger.info("Adding {} IRQs...".format(colorer("reserved")))
416 for name, n in reserved_irqs.items():
417 self.add(name, n)
418
419 self.logger.info(colorer("IRQ Handler created.", color="cyan"))
420
421 # Str ------------------------------------------------------------------------------------------
422 def __str__(self):
423 r ="IRQ Handler (up to {} Locations).".format(colorer(self.n_locs))
424 r += SoCLocHandler.__str__(self)
425 r = r[:-1]
426 return r
427
428 # SoCController ------------------------------------------------------------------------------------
429
430 class SoCController(Module, AutoCSR):
431 def __init__(self):
432 self._reset = CSRStorage(1, description="""
433 Write a ``1`` to this register to reset the SoC.""")
434 self._scratch = CSRStorage(32, reset=0x12345678, description="""
435 Use this register as a scratch space to verify that software read/write accesses
436 to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578
437 can be used to verify endianness.""")
438 self._bus_errors = CSRStatus(32, description="""
439 Total number of Wishbone bus errors (timeouts) since last reset.""")
440
441 # # #
442
443 # Reset
444 self.reset = Signal()
445 self.comb += self.reset.eq(self._reset.re)
446
447 # Bus errors
448 self.bus_error = Signal()
449 bus_errors = Signal(32)
450 self.sync += \
451 If(bus_errors != (2**len(bus_errors)-1),
452 If(self.bus_error, bus_errors.eq(bus_errors + 1))
453 )
454 self.comb += self._bus_errors.status.eq(bus_errors)
455
456 # SoC ----------------------------------------------------------------------------------------------
457
458 class SoC(Module):
459 def __init__(self,
460 bus_standard = "wishbone",
461 bus_data_width = 32,
462 bus_address_width = 32,
463 bus_timeout = 1e6,
464 bus_reserved_regions = {},
465
466 csr_data_width = 32,
467 csr_address_width = 14,
468 csr_alignment = 32,
469 csr_paging = 0x800,
470 csr_reserved_csrs = {},
471
472 irq_n_irqs = 32,
473 irq_reserved_irqs = {},
474 ):
475
476 self.logger = logging.getLogger("SoC")
477 self.logger.info(colorer(" __ _ __ _ __ ", color="bright"))
478 self.logger.info(colorer(" / / (_) /____ | |/_/ ", color="bright"))
479 self.logger.info(colorer(" / /__/ / __/ -_)> < ", color="bright"))
480 self.logger.info(colorer(" /____/_/\\__/\\__/_/|_| ", color="bright"))
481 self.logger.info(colorer(" Build your hardware, easily!", color="bright"))
482
483 self.logger.info(colorer("-"*80, color="bright"))
484 self.logger.info(colorer("Creating new SoC... ({})".format(buildtime()), color="cyan"))
485 self.logger.info(colorer("-"*80, color="bright"))
486
487 # SoC Bus Handler --------------------------------------------------------------------------
488 self.bus = SoCBusHandler(
489 standard = bus_standard,
490 data_width = bus_data_width,
491 address_width = bus_address_width,
492 timeout = bus_timeout,
493 reserved_regions = bus_reserved_regions,
494 )
495
496 # SoC Bus Handler --------------------------------------------------------------------------
497 self.csr = SoCCSRHandler(
498 data_width = csr_data_width,
499 address_width = csr_address_width,
500 alignment = csr_alignment,
501 paging = csr_paging,
502 reserved_csrs = csr_reserved_csrs,
503 )
504
505 # SoC IRQ Handler --------------------------------------------------------------------------
506 self.irq = SoCIRQHandler(
507 n_irqs = irq_n_irqs,
508 reserved_irqs = irq_reserved_irqs
509 )
510
511 self.logger.info(colorer("-"*80, color="bright"))
512 self.logger.info(colorer("Initial SoC:", color="cyan"))
513 self.logger.info(colorer("-"*80, color="bright"))
514 self.logger.info(self.bus)
515 self.logger.info(self.csr)
516 self.logger.info(self.irq)
517 self.logger.info(colorer("-"*80, color="bright"))
518
519
520 def do_finalize(self):
521 self.logger.info(colorer("-"*80, color="bright"))
522 self.logger.info(colorer("Finalized SoC:", color="cyan"))
523 self.logger.info(colorer("-"*80, color="bright"))
524 self.logger.info(self.bus)
525 self.logger.info(self.csr)
526 self.logger.info(self.irq)
527 self.logger.info(colorer("-"*80, color="bright"))
528
529 # SoC Bus Interconnect ---------------------------------------------------------------------
530 bus_masters = self.bus.masters.values()
531 bus_slaves = [(self.bus.regions[n].decoder(), s) for n, s in self.bus.slaves.items()]
532 if len(bus_masters) and len(bus_slaves):
533 self.submodules.bus_interconnect = wishbone.InterconnectShared(
534 masters = bus_masters,
535 slaves = bus_slaves,
536 register = True,
537 timeout_cycles = self.bus.timeout)
538
539 #exit()
540
541 # Test (FIXME: move to litex/text and improve) -----------------------------------------------------
542
543 if __name__ == "__main__":
544 bus = SoCBusHandler("wishbone", reserved_regions={
545 "rom": SoCRegion(origin=0x00000100, size=1024),
546 "ram": SoCRegion(size=512),
547 }
548 )
549 bus.add_master("cpu", None)
550 bus.add_slave("rom", None, SoCRegion(size=1024))
551 bus.add_slave("ram", None, SoCRegion(size=1024))
552
553
554 csr = SoCCSRHandler(reserved_csrs={"ctrl": 0, "uart": 1})
555 csr.add("csr0")
556 csr.add("csr1", 0)
557 #csr.add("csr2", 46)
558 csr.add("csr3", -1)
559 print(bus)
560 print(csr)
561
562 irq = SoCIRQHandler(reserved_irqs={"uart": 1})
563
564 soc = SoC()