3 # This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
12 from litex
.soc
.interconnect
.csr
import *
13 from litex
.soc
.interconnect
import wishbone
16 # - replace raise with exit on logging error.
17 # - add configurable CSR paging.
18 # - manage IO/Linker regions.
20 logging
.basicConfig(level
=logging
.INFO
)
22 # Helpers ------------------------------------------------------------------------------------------
23 def colorer(s
, color
="bright"):
30 "underline": "\x1b[4m"}[color
]
32 return header
+ str(s
) + trailer
34 def buildtime(with_time
=True):
35 fmt
= "%Y-%m-%d %H:%M:%S" if with_time
else "%Y-%m-%d"
36 return datetime
.datetime
.fromtimestamp(time
.time()).strftime("%Y-%m-%d %H:%M:%S")
38 # SoCRegion ----------------------------------------------------------------------------------------
41 def __init__(self
, origin
=None, size
=None, cached
=True):
42 self
.logger
= logging
.getLogger("SoCRegion")
51 size
= 2**log2_int(size
, False)
52 if (origin
& (size
- 1)) != 0:
53 self
.logger
.error("Origin needs to be aligned on size:")
54 self
.logger
.error(self
)
56 origin
>>= 2 # bytes to words aligned
57 size
>>= 2 # bytes to words aligned
58 return lambda a
: (a
[log2_int(size
):-1] == (origin
>> log2_int(size
)))
62 if self
.origin
is not None:
63 r
+= "Origin: {}, ".format(colorer("0x{:08x}".format(self
.origin
)))
64 if self
.size
is not None:
65 r
+= "Size: {}, ".format(colorer("0x{:08x}".format(self
.size
)))
66 r
+= "Cached: {}".format(colorer(self
.cached
))
70 class SoCLinkerRegion(SoCRegion
):
73 # SoCBusHandler ------------------------------------------------------------------------------------
76 supported_standard
= ["wishbone"]
77 supported_data_width
= [32, 64]
78 supported_address_width
= [32]
80 # Creation -------------------------------------------------------------------------------------
81 def __init__(self
, standard
, data_width
=32, address_width
=32, timeout
=1e6
, reserved_regions
={}):
82 self
.logger
= logging
.getLogger("SoCBusHandler")
83 self
.logger
.info(colorer("Creating new Bus Handler...", color
="cyan"))
86 if standard
not in self
.supported_standard
:
87 self
.logger
.error("Unsupported Standard: {} supporteds: {:s}".format(
88 colorer(standard
, color
="red"),
89 colorer(", ".join(self
.supported_standard
), color
="green")))
93 if data_width
not in self
.supported_data_width
:
94 self
.logger
.error("Unsupported Data_Width: {} supporteds: {:s}".format(
95 colorer(data_width
, color
="red"),
96 colorer(", ".join(str(x
) for x
in self
.supported_data_width
), color
="green")))
100 if address_width
not in self
.supported_address_width
:
101 self
.logger
.error("Unsupported Address Width: {} supporteds: {:s}".format(
102 colorer(data_width
, color
="red"),
103 colorer(", ".join(str(x
) for x
in self
.supported_address_width
), color
="green")))
107 self
.standard
= standard
108 self
.data_width
= data_width
109 self
.address_width
= address_width
113 self
.timeout
= timeout
114 self
.logger
.info("{}-bit {} Bus, {}GiB Address Space.".format(
115 colorer(data_width
), colorer(standard
), colorer(2**address_width
/2**30)))
117 # Adding reserved regions
118 self
.logger
.info("Adding {} Regions...".format(colorer("reserved")))
119 for name
, region
in reserved_regions
.items():
120 if isinstance(region
, int):
121 region
= SoCRegion(origin
=region
, size
=0x1000000)
122 self
.add_region(name
, region
)
124 self
.logger
.info(colorer("Bus Handler created.", color
="cyan"))
126 # Add/Allog/Check Regions ----------------------------------------------------------------------
127 def add_region(self
, name
, region
):
129 # Check if SoCLinkerRegion
130 if isinstance(region
, SoCLinkerRegion
):
131 self
.logger
.info("FIXME: SoCLinkerRegion")
133 elif isinstance(region
, SoCRegion
):
134 # If no origin specified, allocate region.
135 if region
.origin
is None:
137 region
= self
.alloc_region(region
.size
, region
.cached
)
138 self
.regions
[name
] = region
139 # Else add region and check for overlaps.
141 self
.regions
[name
] = region
142 overlap
= self
.check_region(self
.regions
)
143 if overlap
is not None:
144 self
.logger
.error("Region overlap between {} and {}:".format(
145 colorer(overlap
[0], color
="red"),
146 colorer(overlap
[1], color
="red")))
147 self
.logger
.error(str(self
.regions
[overlap
[0]]))
148 self
.logger
.error(str(self
.regions
[overlap
[1]]))
150 self
.logger
.info("{} Region {} {}.".format(
151 colorer(name
, color
="underline"),
152 colorer("allocated" if allocated
else "added", color
="yellow" if allocated
else "green"),
155 self
.logger
.error("{} is not a supported Region".format(colorer(name
, color
="red")))
158 def alloc_region(self
, size
, cached
=True):
159 self
.logger
.info("Allocating {} Region of size {}...".format(
160 colorer("Cached" if cached
else "IO"),
161 colorer("0x{:08x}".format(size
))))
163 # Limit Search Regions
164 uncached_regions
= {}
165 for _
, region
in self
.regions
.items():
166 if region
.cached
== False:
167 uncached_regions
[name
] = region
169 search_regions
= uncached_regions
171 search_regions
= {"main": SoCRegion(origin
=0x00000000, size
=2**self
.address_width
-1)}
173 # Iterate on Search_Regions to find a Candidate
174 for _
, search_region
in search_regions
.items():
175 origin
= search_region
.origin
176 while (origin
+ size
) < (search_region
.origin
+ search_region
.size
):
177 # Create a Candicate.
178 candidate
= SoCRegion(origin
=origin
, size
=size
, cached
=cached
)
180 # Check Candidate does not overlap with allocated existing regions
181 for _
, allocated
in self
.regions
.items():
182 if self
.check_region({"0": allocated
, "1": candidate
}) is not None:
183 origin
= allocated
.origin
+ allocated
.size
187 # If no overlap, the Candidate is selected
190 self
.logger
.error("Not enough Address Space to allocate Region")
193 def check_region(self
, regions
):
195 while i
< len(regions
):
196 n0
= list(regions
.keys())[i
]
198 for n1
in list(regions
.keys())[i
+1:]:
200 if isinstance(r0
, SoCLinkerRegion
) or isinstance(r1
, SoCLinkerRegion
):
202 if r0
.origin
>= (r1
.origin
+ r1
.size
):
204 if r1
.origin
>= (r0
.origin
+ r0
.size
):
210 # Add Master/Slave -----------------------------------------------------------------------------
211 def add_master(self
, name
=None, master
=None, io_regions
={}):
213 name
= "master{:d}".format(len(self
.masters
))
214 if name
in self
.masters
.keys():
215 self
.logger
.error("{} already declared as Bus Master:".format(colorer(name
, color
="red")))
216 self
.logger
.error(self
)
218 self
.masters
[name
] = master
219 self
.logger
.info("{} {} as Bus Master.".format(colorer(name
, color
="underline"), colorer("added", color
="green")))
220 # FIXME: handle IO regions
222 def add_slave(self
, name
=None, slave
=None, region
=None):
223 no_name
= name
is None
224 no_region
= region
is None
225 if no_name
and no_region
:
226 self
.logger
.error("Please specify at least {} or {} of Bus Slave".format(
227 colorer("name", color
="red"),
228 colorer("region", color
="red")))
231 name
= "slave{:d}".format(len(self
.slaves
))
233 region
= self
.regions
.get(name
, None)
235 self
.logger
.error("Unable to find Region {}".format(colorer(name
, color
="red")))
238 self
.add_region(name
, region
)
239 if name
in self
.slaves
.keys():
240 self
.logger
.error("{} already declared as Bus Slave:".format(colorer(name
, color
="red")))
241 self
.logger
.error(self
)
243 self
.slaves
[name
] = slave
244 self
.logger
.info("{} {} as Bus Slave.".format(
245 colorer(name
, color
="underline"),
246 colorer("added", color
="green")))
248 # Str ------------------------------------------------------------------------------------------
250 r
= "{}-bit {} Bus, {}GiB Address Space.\n".format(
251 colorer(self
.data_width
), colorer(self
.standard
), colorer(2**self
.address_width
/2**30))
252 r
+= "Bus Regions: ({})\n".format(len(self
.regions
.keys())) if len(self
.regions
.keys()) else ""
253 for name
, region
in self
.regions
.items():
254 r
+= colorer(name
, color
="underline") + " "*(20-len(name
)) + ": " + str(region
) + "\n"
255 r
+= "Bus Masters: ({})\n".format(len(self
.masters
.keys())) if len(self
.masters
.keys()) else ""
256 for name
in self
.masters
.keys():
257 r
+= "- {}\n".format(colorer(name
, color
="underline"))
258 r
+= "Bus Slaves: ({})\n".format(len(self
.slaves
.keys())) if len(self
.slaves
.keys()) else ""
259 for name
in self
.slaves
.keys():
260 r
+= "- {}\n".format(colorer(name
, color
="underline"))
264 # SoCLocHandler --------------------------------------------------------------------------------------
267 # Creation -------------------------------------------------------------------------------------
268 def __init__(self
, name
, n_locs
):
273 # Add ------------------------------------------------------------------------------------------
274 def add(self
, name
, n
=None, use_loc_if_exists
=False):
276 if not (use_loc_if_exists
and name
in self
.locs
.keys()):
277 if name
in self
.locs
.keys():
278 self
.logger
.error("{} {} name already used.".format(colorer(name
, "red"), self
.name
))
279 self
.logger
.error(self
)
281 if n
in self
.locs
.values():
282 self
.logger
.error("{} {} Location already used.".format(colorer(n
, "red"), self
.name
))
283 self
.logger
.error(self
)
290 self
.logger
.error("{} {} Location should be positive.".format(
291 colorer(n
, color
="red"),
295 self
.logger
.error("{} {} Location too high (Up to {}).".format(
296 colorer(n
, color
="red"),
298 colorer(self
.n_csrs
, color
="green")))
303 self
.logger
.info("{} {} {} at Location {}.".format(
304 colorer(name
, color
="underline"),
306 colorer("allocated" if allocated
else "added", color
="yellow" if allocated
else "green"),
309 # Alloc ----------------------------------------------------------------------------------------
310 def alloc(self
, name
):
311 for n
in range(self
.n_locs
):
312 if n
not in self
.locs
.values():
314 self
.logger
.error("Not enough Locations.")
315 self
.logger
.error(self
)
318 # Str ------------------------------------------------------------------------------------------
320 r
= "{} Locations: ({})\n".format(self
.name
, len(self
.locs
.keys())) if len(self
.locs
.keys()) else ""
321 for name
in self
.locs
.keys():
322 r
+= "- {}{}: {}\n".format(colorer(name
, color
="underline"), " "*(20-len(name
)), colorer(self
.locs
[name
]))
325 # SoCCSRHandler ------------------------------------------------------------------------------------
327 class SoCCSRHandler(SoCLocHandler
):
328 supported_data_width
= [8, 32]
329 supported_address_width
= [14, 15]
330 supported_alignment
= [32, 64]
331 supported_paging
= [0x800]
333 # Creation -------------------------------------------------------------------------------------
334 def __init__(self
, data_width
=32, address_width
=14, alignment
=32, paging
=0x800, reserved_csrs
={}):
335 SoCLocHandler
.__init
__(self
, "CSR", n_locs
=4*2**address_width
//paging
) # FIXME
336 self
.logger
= logging
.getLogger("SoCCSRHandler")
337 self
.logger
.info(colorer("Creating new CSR Handler...", color
="cyan"))
340 if data_width
not in self
.supported_data_width
:
341 self
.logger
.error("Unsupported data_width: {} supporteds: {:s}".format(
342 colorer(data_width
, color
="red"),
343 colorer(", ".join(str(x
) for x
in self
.supported_data_width
)), color
="green"))
346 # Check Address Width
347 if address_width
not in self
.supported_address_width
:
348 self
.logger
.error("Unsupported address_width: {} supporteds: {:s}".format(
349 colorer(address_width
, color
="red"),
350 colorer(", ".join(str(x
) for x
in self
.supported_address_width
), color
="green")))
354 if alignment
not in self
.supported_alignment
:
355 self
.logger
.error("Unsupported alignment: {} supporteds: {:s}".format(
356 colorer(alignment
, color
="red"),
357 colorer(", ".join(str(x
) for x
in self
.supported_alignment
), color
="green")))
361 if paging
not in self
.supported_paging
:
362 self
.logger
.error("Unsupported paging: {} supporteds: {:s}".format(
363 colorer(paging
, color
="red"),
364 colorer(", ".join(str(x
) for x
in self
.supported_paging
), color
="green")))
368 self
.data_width
= data_width
369 self
.address_width
= address_width
370 self
.alignment
= alignment
372 self
.logger
.info("{}-bit CSR Bus, {}KiB Address Space, {}B Paging (Up to {} Locations).\n".format(
373 colorer(self
.data_width
),
374 colorer(2**self
.address_width
/2**10),
375 colorer(self
.paging
),
376 colorer(self
.n_locs
)))
378 # Adding reserved CSRs
379 self
.logger
.info("Adding {} CSRs...".format(colorer("reserved")))
380 for name
, n
in reserved_csrs
.items():
383 self
.logger
.info(colorer("CSR Bus Handler created.", color
="cyan"))
385 # Str ------------------------------------------------------------------------------------------
387 r
= "{}-bit CSR Bus, {}KiB Address Space, {}B Paging (Up to {} Locations).\n".format(
388 colorer(self
.data_width
),
389 colorer(2**self
.address_width
/2**10),
390 colorer(self
.paging
),
391 colorer(self
.n_locs
))
392 r
+= SoCLocHandler
.__str
__(self
)
396 # SoCIRQHandler ------------------------------------------------------------------------------------
398 class SoCIRQHandler(SoCLocHandler
):
399 # Creation -------------------------------------------------------------------------------------
400 def __init__(self
, n_irqs
=32, reserved_irqs
={}):
401 SoCLocHandler
.__init
__(self
, "IRQ", n_locs
=n_irqs
)
402 self
.logger
= logging
.getLogger("SoCIRQHandler")
403 self
.logger
.info(colorer("Creating new SoC IRQ Handler...", color
="cyan"))
407 self
.logger
.error("Unsupported IRQs number: {} supporteds: {:s}".format(
408 colorer(n
, color
="red"), colorer("Up to 32", color
="green")))
412 self
.logger
.info("IRQ Handler (up to {} Locations).".format(colorer(n_irqs
)))
414 # Adding reserved IRQs
415 self
.logger
.info("Adding {} IRQs...".format(colorer("reserved")))
416 for name
, n
in reserved_irqs
.items():
419 self
.logger
.info(colorer("IRQ Handler created.", color
="cyan"))
421 # Str ------------------------------------------------------------------------------------------
423 r
="IRQ Handler (up to {} Locations).\n".format(colorer(self
.n_locs
))
424 r
+= SoCLocHandler
.__str
__(self
)
428 # SoCController ------------------------------------------------------------------------------------
430 class SoCController(Module
, AutoCSR
):
432 self
._reset
= CSRStorage(1, description
="""
433 Write a ``1`` to this register to reset the SoC.""")
434 self
._scratch
= CSRStorage(32, reset
=0x12345678, description
="""
435 Use this register as a scratch space to verify that software read/write accesses
436 to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578
437 can be used to verify endianness.""")
438 self
._bus
_errors
= CSRStatus(32, description
="""
439 Total number of Wishbone bus errors (timeouts) since last reset.""")
444 self
.reset
= Signal()
445 self
.comb
+= self
.reset
.eq(self
._reset
.re
)
448 self
.bus_error
= Signal()
449 bus_errors
= Signal(32)
451 If(bus_errors
!= (2**len(bus_errors
)-1),
452 If(self
.bus_error
, bus_errors
.eq(bus_errors
+ 1))
454 self
.comb
+= self
._bus
_errors
.status
.eq(bus_errors
)
456 # SoC ----------------------------------------------------------------------------------------------
460 bus_standard
= "wishbone",
462 bus_address_width
= 32,
464 bus_reserved_regions
= {},
467 csr_address_width
= 14,
470 csr_reserved_csrs
= {},
473 irq_reserved_irqs
= {},
476 self
.logger
= logging
.getLogger("SoC")
477 self
.logger
.info(colorer(" __ _ __ _ __ ", color
="bright"))
478 self
.logger
.info(colorer(" / / (_) /____ | |/_/ ", color
="bright"))
479 self
.logger
.info(colorer(" / /__/ / __/ -_)> < ", color
="bright"))
480 self
.logger
.info(colorer(" /____/_/\\__/\\__/_/|_| ", color
="bright"))
481 self
.logger
.info(colorer(" Build your hardware, easily!", color
="bright"))
483 self
.logger
.info(colorer("-"*80, color
="bright"))
484 self
.logger
.info(colorer("Creating new SoC... ({})".format(buildtime()), color
="cyan"))
485 self
.logger
.info(colorer("-"*80, color
="bright"))
487 # SoC Bus Handler --------------------------------------------------------------------------
488 self
.bus
= SoCBusHandler(
489 standard
= bus_standard
,
490 data_width
= bus_data_width
,
491 address_width
= bus_address_width
,
492 timeout
= bus_timeout
,
493 reserved_regions
= bus_reserved_regions
,
496 # SoC Bus Handler --------------------------------------------------------------------------
497 self
.csr
= SoCCSRHandler(
498 data_width
= csr_data_width
,
499 address_width
= csr_address_width
,
500 alignment
= csr_alignment
,
502 reserved_csrs
= csr_reserved_csrs
,
505 # SoC IRQ Handler --------------------------------------------------------------------------
506 self
.irq
= SoCIRQHandler(
508 reserved_irqs
= irq_reserved_irqs
511 self
.logger
.info(colorer("-"*80, color
="bright"))
512 self
.logger
.info(colorer("Initial SoC:", color
="cyan"))
513 self
.logger
.info(colorer("-"*80, color
="bright"))
514 self
.logger
.info(self
.bus
)
515 self
.logger
.info(self
.csr
)
516 self
.logger
.info(self
.irq
)
517 self
.logger
.info(colorer("-"*80, color
="bright"))
520 def do_finalize(self
):
521 self
.logger
.info(colorer("-"*80, color
="bright"))
522 self
.logger
.info(colorer("Finalized SoC:", color
="cyan"))
523 self
.logger
.info(colorer("-"*80, color
="bright"))
524 self
.logger
.info(self
.bus
)
525 self
.logger
.info(self
.csr
)
526 self
.logger
.info(self
.irq
)
527 self
.logger
.info(colorer("-"*80, color
="bright"))
529 # SoC Bus Interconnect ---------------------------------------------------------------------
530 bus_masters
= self
.bus
.masters
.values()
531 bus_slaves
= [(self
.bus
.regions
[n
].decoder(), s
) for n
, s
in self
.bus
.slaves
.items()]
532 if len(bus_masters
) and len(bus_slaves
):
533 self
.submodules
.bus_interconnect
= wishbone
.InterconnectShared(
534 masters
= bus_masters
,
537 timeout_cycles
= self
.bus
.timeout
)
541 # Test (FIXME: move to litex/text and improve) -----------------------------------------------------
543 if __name__
== "__main__":
544 bus
= SoCBusHandler("wishbone", reserved_regions
={
545 "rom": SoCRegion(origin
=0x00000100, size
=1024),
546 "ram": SoCRegion(size
=512),
549 bus
.add_master("cpu", None)
550 bus
.add_slave("rom", None, SoCRegion(size
=1024))
551 bus
.add_slave("ram", None, SoCRegion(size
=1024))
554 csr
= SoCCSRHandler(reserved_csrs
={"ctrl": 0, "uart": 1})
562 irq
= SoCIRQHandler(reserved_irqs
={"uart": 1})