3 # This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
12 from litex
.soc
.interconnect
.csr
import *
13 from litex
.soc
.interconnect
import wishbone
16 # - replace raise with exit on logging error.
17 # - add configurable CSR paging.
18 # - manage IO/Linker regions.
20 logging
.basicConfig(level
=logging
.INFO
)
22 # Helpers ------------------------------------------------------------------------------------------
23 def colorer(s
, color
="bright"):
30 "underline": "\x1b[4m"}[color
]
32 return header
+ str(s
) + trailer
34 def buildtime(with_time
=True):
35 fmt
= "%Y-%m-%d %H:%M:%S" if with_time
else "%Y-%m-%d"
36 return datetime
.datetime
.fromtimestamp(time
.time()).strftime("%Y-%m-%d %H:%M:%S")
38 # SoCRegion ----------------------------------------------------------------------------------------
41 def __init__(self
, origin
=None, size
=None, cached
=True):
42 self
.logger
= logging
.getLogger("SoCRegion")
51 size
= 2**log2_int(size
, False)
52 if (origin
& (size
- 1)) != 0:
53 self
.logger
.error("Origin needs to be aligned on size:")
54 self
.logger
.error(self
)
56 origin
>>= 2 # bytes to words aligned
57 size
>>= 2 # bytes to words aligned
58 return lambda a
: (a
[log2_int(size
):-1] == (origin
>> log2_int(size
)))
62 if self
.origin
is not None:
63 r
+= "Origin: {}, ".format(colorer("0x{:08x}".format(self
.origin
)))
64 if self
.size
is not None:
65 r
+= "Size: {}, ".format(colorer("0x{:08x}".format(self
.size
)))
66 r
+= "Cached: {}".format(colorer(self
.cached
))
70 class SoCLinkerRegion(SoCRegion
):
73 # SoCBusHandler ------------------------------------------------------------------------------------
75 class SoCBusHandler(Module
):
76 supported_standard
= ["wishbone"]
77 supported_data_width
= [32, 64]
78 supported_address_width
= [32]
80 # Creation -------------------------------------------------------------------------------------
81 def __init__(self
, standard
, data_width
=32, address_width
=32, timeout
=1e6
, reserved_regions
={}):
82 self
.logger
= logging
.getLogger("SoCBusHandler")
83 self
.logger
.info(colorer("Creating new Bus Handler...", color
="cyan"))
86 if standard
not in self
.supported_standard
:
87 self
.logger
.error("Unsupported Standard: {} supporteds: {:s}".format(
88 colorer(standard
, color
="red"),
89 colorer(", ".join(self
.supported_standard
), color
="green")))
93 if data_width
not in self
.supported_data_width
:
94 self
.logger
.error("Unsupported Data_Width: {} supporteds: {:s}".format(
95 colorer(data_width
, color
="red"),
96 colorer(", ".join(str(x
) for x
in self
.supported_data_width
), color
="green")))
100 if address_width
not in self
.supported_address_width
:
101 self
.logger
.error("Unsupported Address Width: {} supporteds: {:s}".format(
102 colorer(data_width
, color
="red"),
103 colorer(", ".join(str(x
) for x
in self
.supported_address_width
), color
="green")))
107 self
.standard
= standard
108 self
.data_width
= data_width
109 self
.address_width
= address_width
113 self
.timeout
= timeout
114 self
.logger
.info("{}-bit {} Bus, {}GiB Address Space.".format(
115 colorer(data_width
), colorer(standard
), colorer(2**address_width
/2**30)))
117 # Adding reserved regions
118 self
.logger
.info("Adding {} Regions...".format(colorer("reserved")))
119 for name
, region
in reserved_regions
.items():
120 if isinstance(region
, int):
121 region
= SoCRegion(origin
=region
, size
=0x1000000)
122 self
.add_region(name
, region
)
124 self
.logger
.info(colorer("Bus Handler created.", color
="cyan"))
126 # Add/Allog/Check Regions ----------------------------------------------------------------------
127 def add_region(self
, name
, region
):
129 # Check if SoCLinkerRegion
130 if isinstance(region
, SoCLinkerRegion
):
131 self
.logger
.info("FIXME: SoCLinkerRegion")
133 elif isinstance(region
, SoCRegion
):
134 # If no origin specified, allocate region.
135 if region
.origin
is None:
137 region
= self
.alloc_region(region
.size
, region
.cached
)
138 self
.regions
[name
] = region
139 # Else add region and check for overlaps.
141 self
.regions
[name
] = region
142 overlap
= self
.check_region(self
.regions
)
143 if overlap
is not None:
144 self
.logger
.error("Region overlap between {} and {}:".format(
145 colorer(overlap
[0], color
="red"),
146 colorer(overlap
[1], color
="red")))
147 self
.logger
.error(str(self
.regions
[overlap
[0]]))
148 self
.logger
.error(str(self
.regions
[overlap
[1]]))
150 self
.logger
.info("{} Region {} {}.".format(
151 colorer(name
, color
="underline"),
152 colorer("allocated" if allocated
else "added", color
="yellow" if allocated
else "green"),
155 self
.logger
.error("{} is not a supported Region".format(colorer(name
, color
="red")))
158 def alloc_region(self
, size
, cached
=True):
159 self
.logger
.info("Allocating {} Region of size {}...".format(
160 colorer("Cached" if cached
else "IO"),
161 colorer("0x{:08x}".format(size
))))
163 # Limit Search Regions
164 uncached_regions
= {}
165 for _
, region
in self
.regions
.items():
166 if region
.cached
== False:
167 uncached_regions
[name
] = region
169 search_regions
= uncached_regions
171 search_regions
= {"main": SoCRegion(origin
=0x00000000, size
=2**self
.address_width
-1)}
173 # Iterate on Search_Regions to find a Candidate
174 for _
, search_region
in search_regions
.items():
175 origin
= search_region
.origin
176 while (origin
+ size
) < (search_region
.origin
+ search_region
.size
):
177 # Create a Candicate.
178 candidate
= SoCRegion(origin
=origin
, size
=size
, cached
=cached
)
180 # Check Candidate does not overlap with allocated existing regions
181 for _
, allocated
in self
.regions
.items():
182 if self
.check_region({"0": allocated
, "1": candidate
}) is not None:
183 origin
= allocated
.origin
+ allocated
.size
187 # If no overlap, the Candidate is selected
190 self
.logger
.error("Not enough Address Space to allocate Region")
193 def check_region(self
, regions
):
195 while i
< len(regions
):
196 n0
= list(regions
.keys())[i
]
198 for n1
in list(regions
.keys())[i
+1:]:
200 if isinstance(r0
, SoCLinkerRegion
) or isinstance(r1
, SoCLinkerRegion
):
202 if r0
.origin
>= (r1
.origin
+ r1
.size
):
204 if r1
.origin
>= (r0
.origin
+ r0
.size
):
210 # Add Master/Slave -----------------------------------------------------------------------------
211 def add_master(self
, name
=None, master
=None, io_regions
={}):
213 name
= "master{:d}".format(len(self
.masters
))
214 if name
in self
.masters
.keys():
215 self
.logger
.error("{} already declared as Bus Master:".format(colorer(name
, color
="red")))
216 self
.logger
.error(self
)
218 if master
.data_width
!= self
.data_width
:
219 self
.logger
.error("{} Bus Master {} from {}-bit to {}-bit.".format(
221 colorer("converted", color
="yellow"),
222 colorer(master
.data_width
),
223 colorer(self
.data_width
)))
224 new_master
= wishbone
.Interface(data_width
=self
.data_width
)
225 self
.submodules
+= wishbone
.Converter(master
, new_master
)
227 self
.masters
[name
] = master
228 self
.logger
.info("{} {} as Bus Master.".format(colorer(name
, color
="underline"), colorer("added", color
="green")))
229 # FIXME: handle IO regions
231 def add_slave(self
, name
=None, slave
=None, region
=None):
232 no_name
= name
is None
233 no_region
= region
is None
234 if no_name
and no_region
:
235 self
.logger
.error("Please specify at least {} or {} of Bus Slave".format(
236 colorer("name", color
="red"),
237 colorer("region", color
="red")))
240 name
= "slave{:d}".format(len(self
.slaves
))
242 region
= self
.regions
.get(name
, None)
244 self
.logger
.error("Unable to find Region {}".format(colorer(name
, color
="red")))
247 self
.add_region(name
, region
)
248 if name
in self
.slaves
.keys():
249 self
.logger
.error("{} already declared as Bus Slave:".format(colorer(name
, color
="red")))
250 self
.logger
.error(self
)
252 if slave
.data_width
!= self
.data_width
:
253 self
.logger
.error("{} Bus Slave {} from {}-bit to {}-bit.".format(
255 colorer("converted", color
="yellow"),
256 colorer(slave
.data_width
),
257 colorer(self
.data_width
)))
258 new_slave
= wishbone
.Interface(data_width
=self
.data_width
)
259 self
.submodules
+= wishbone
.Converter(slave
, new_slave
)
261 self
.slaves
[name
] = slave
262 self
.logger
.info("{} {} as Bus Slave.".format(
263 colorer(name
, color
="underline"),
264 colorer("added", color
="green")))
266 # Str ------------------------------------------------------------------------------------------
268 r
= "{}-bit {} Bus, {}GiB Address Space.\n".format(
269 colorer(self
.data_width
), colorer(self
.standard
), colorer(2**self
.address_width
/2**30))
270 r
+= "Bus Regions: ({})\n".format(len(self
.regions
.keys())) if len(self
.regions
.keys()) else ""
271 for name
, region
in self
.regions
.items():
272 r
+= colorer(name
, color
="underline") + " "*(20-len(name
)) + ": " + str(region
) + "\n"
273 r
+= "Bus Masters: ({})\n".format(len(self
.masters
.keys())) if len(self
.masters
.keys()) else ""
274 for name
in self
.masters
.keys():
275 r
+= "- {}\n".format(colorer(name
, color
="underline"))
276 r
+= "Bus Slaves: ({})\n".format(len(self
.slaves
.keys())) if len(self
.slaves
.keys()) else ""
277 for name
in self
.slaves
.keys():
278 r
+= "- {}\n".format(colorer(name
, color
="underline"))
282 # SoCLocHandler --------------------------------------------------------------------------------------
284 class SoCLocHandler(Module
):
285 # Creation -------------------------------------------------------------------------------------
286 def __init__(self
, name
, n_locs
):
291 # Add ------------------------------------------------------------------------------------------
292 def add(self
, name
, n
=None, use_loc_if_exists
=False):
294 if not (use_loc_if_exists
and name
in self
.locs
.keys()):
295 if name
in self
.locs
.keys():
296 self
.logger
.error("{} {} name already used.".format(colorer(name
, "red"), self
.name
))
297 self
.logger
.error(self
)
299 if n
in self
.locs
.values():
300 self
.logger
.error("{} {} Location already used.".format(colorer(n
, "red"), self
.name
))
301 self
.logger
.error(self
)
308 self
.logger
.error("{} {} Location should be positive.".format(
309 colorer(n
, color
="red"),
313 self
.logger
.error("{} {} Location too high (Up to {}).".format(
314 colorer(n
, color
="red"),
316 colorer(self
.n_csrs
, color
="green")))
321 self
.logger
.info("{} {} {} at Location {}.".format(
322 colorer(name
, color
="underline"),
324 colorer("allocated" if allocated
else "added", color
="yellow" if allocated
else "green"),
327 # Alloc ----------------------------------------------------------------------------------------
328 def alloc(self
, name
):
329 for n
in range(self
.n_locs
):
330 if n
not in self
.locs
.values():
332 self
.logger
.error("Not enough Locations.")
333 self
.logger
.error(self
)
336 # Str ------------------------------------------------------------------------------------------
338 r
= "{} Locations: ({})\n".format(self
.name
, len(self
.locs
.keys())) if len(self
.locs
.keys()) else ""
339 for name
in self
.locs
.keys():
340 r
+= "- {}{}: {}\n".format(colorer(name
, color
="underline"), " "*(20-len(name
)), colorer(self
.locs
[name
]))
343 # SoCCSRHandler ------------------------------------------------------------------------------------
345 class SoCCSRHandler(SoCLocHandler
):
346 supported_data_width
= [8, 32]
347 supported_address_width
= [14, 15]
348 supported_alignment
= [32, 64]
349 supported_paging
= [0x800]
351 # Creation -------------------------------------------------------------------------------------
352 def __init__(self
, data_width
=32, address_width
=14, alignment
=32, paging
=0x800, reserved_csrs
={}):
353 SoCLocHandler
.__init
__(self
, "CSR", n_locs
=4*2**address_width
//paging
) # FIXME
354 self
.logger
= logging
.getLogger("SoCCSRHandler")
355 self
.logger
.info(colorer("Creating new CSR Handler...", color
="cyan"))
358 if data_width
not in self
.supported_data_width
:
359 self
.logger
.error("Unsupported data_width: {} supporteds: {:s}".format(
360 colorer(data_width
, color
="red"),
361 colorer(", ".join(str(x
) for x
in self
.supported_data_width
)), color
="green"))
364 # Check Address Width
365 if address_width
not in self
.supported_address_width
:
366 self
.logger
.error("Unsupported address_width: {} supporteds: {:s}".format(
367 colorer(address_width
, color
="red"),
368 colorer(", ".join(str(x
) for x
in self
.supported_address_width
), color
="green")))
372 if alignment
not in self
.supported_alignment
:
373 self
.logger
.error("Unsupported alignment: {} supporteds: {:s}".format(
374 colorer(alignment
, color
="red"),
375 colorer(", ".join(str(x
) for x
in self
.supported_alignment
), color
="green")))
379 if paging
not in self
.supported_paging
:
380 self
.logger
.error("Unsupported paging: {} supporteds: {:s}".format(
381 colorer(paging
, color
="red"),
382 colorer(", ".join(str(x
) for x
in self
.supported_paging
), color
="green")))
386 self
.data_width
= data_width
387 self
.address_width
= address_width
388 self
.alignment
= alignment
390 self
.logger
.info("{}-bit CSR Bus, {}KiB Address Space, {}B Paging (Up to {} Locations).\n".format(
391 colorer(self
.data_width
),
392 colorer(2**self
.address_width
/2**10),
393 colorer(self
.paging
),
394 colorer(self
.n_locs
)))
396 # Adding reserved CSRs
397 self
.logger
.info("Adding {} CSRs...".format(colorer("reserved")))
398 for name
, n
in reserved_csrs
.items():
401 self
.logger
.info(colorer("CSR Bus Handler created.", color
="cyan"))
403 # Str ------------------------------------------------------------------------------------------
405 r
= "{}-bit CSR Bus, {}KiB Address Space, {}B Paging (Up to {} Locations).\n".format(
406 colorer(self
.data_width
),
407 colorer(2**self
.address_width
/2**10),
408 colorer(self
.paging
),
409 colorer(self
.n_locs
))
410 r
+= SoCLocHandler
.__str
__(self
)
414 # SoCIRQHandler ------------------------------------------------------------------------------------
416 class SoCIRQHandler(SoCLocHandler
):
417 # Creation -------------------------------------------------------------------------------------
418 def __init__(self
, n_irqs
=32, reserved_irqs
={}):
419 SoCLocHandler
.__init
__(self
, "IRQ", n_locs
=n_irqs
)
420 self
.logger
= logging
.getLogger("SoCIRQHandler")
421 self
.logger
.info(colorer("Creating new SoC IRQ Handler...", color
="cyan"))
425 self
.logger
.error("Unsupported IRQs number: {} supporteds: {:s}".format(
426 colorer(n
, color
="red"), colorer("Up to 32", color
="green")))
430 self
.logger
.info("IRQ Handler (up to {} Locations).".format(colorer(n_irqs
)))
432 # Adding reserved IRQs
433 self
.logger
.info("Adding {} IRQs...".format(colorer("reserved")))
434 for name
, n
in reserved_irqs
.items():
437 self
.logger
.info(colorer("IRQ Handler created.", color
="cyan"))
439 # Str ------------------------------------------------------------------------------------------
441 r
="IRQ Handler (up to {} Locations).\n".format(colorer(self
.n_locs
))
442 r
+= SoCLocHandler
.__str
__(self
)
446 # SoCController ------------------------------------------------------------------------------------
448 class SoCController(Module
, AutoCSR
):
450 self
._reset
= CSRStorage(1, description
="""
451 Write a ``1`` to this register to reset the SoC.""")
452 self
._scratch
= CSRStorage(32, reset
=0x12345678, description
="""
453 Use this register as a scratch space to verify that software read/write accesses
454 to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578
455 can be used to verify endianness.""")
456 self
._bus
_errors
= CSRStatus(32, description
="""
457 Total number of Wishbone bus errors (timeouts) since last reset.""")
462 self
.reset
= Signal()
463 self
.comb
+= self
.reset
.eq(self
._reset
.re
)
466 self
.bus_error
= Signal()
467 bus_errors
= Signal(32)
469 If(bus_errors
!= (2**len(bus_errors
)-1),
470 If(self
.bus_error
, bus_errors
.eq(bus_errors
+ 1))
472 self
.comb
+= self
._bus
_errors
.status
.eq(bus_errors
)
474 # SoC ----------------------------------------------------------------------------------------------
478 bus_standard
= "wishbone",
480 bus_address_width
= 32,
482 bus_reserved_regions
= {},
485 csr_address_width
= 14,
488 csr_reserved_csrs
= {},
491 irq_reserved_irqs
= {},
494 self
.logger
= logging
.getLogger("SoC")
495 self
.logger
.info(colorer(" __ _ __ _ __ ", color
="bright"))
496 self
.logger
.info(colorer(" / / (_) /____ | |/_/ ", color
="bright"))
497 self
.logger
.info(colorer(" / /__/ / __/ -_)> < ", color
="bright"))
498 self
.logger
.info(colorer(" /____/_/\\__/\\__/_/|_| ", color
="bright"))
499 self
.logger
.info(colorer(" Build your hardware, easily!", color
="bright"))
501 self
.logger
.info(colorer("-"*80, color
="bright"))
502 self
.logger
.info(colorer("Creating new SoC... ({})".format(buildtime()), color
="cyan"))
503 self
.logger
.info(colorer("-"*80, color
="bright"))
505 # SoC Bus Handler --------------------------------------------------------------------------
506 self
.submodules
.bus
= SoCBusHandler(
507 standard
= bus_standard
,
508 data_width
= bus_data_width
,
509 address_width
= bus_address_width
,
510 timeout
= bus_timeout
,
511 reserved_regions
= bus_reserved_regions
,
514 # SoC Bus Handler --------------------------------------------------------------------------
515 self
.submodules
.csr
= SoCCSRHandler(
516 data_width
= csr_data_width
,
517 address_width
= csr_address_width
,
518 alignment
= csr_alignment
,
520 reserved_csrs
= csr_reserved_csrs
,
523 # SoC IRQ Handler --------------------------------------------------------------------------
524 self
.submodules
.irq
= SoCIRQHandler(
526 reserved_irqs
= irq_reserved_irqs
529 self
.logger
.info(colorer("-"*80, color
="bright"))
530 self
.logger
.info(colorer("Initial SoC:", color
="cyan"))
531 self
.logger
.info(colorer("-"*80, color
="bright"))
532 self
.logger
.info(self
.bus
)
533 self
.logger
.info(self
.csr
)
534 self
.logger
.info(self
.irq
)
535 self
.logger
.info(colorer("-"*80, color
="bright"))
537 def do_finalize(self
):
538 self
.logger
.info(colorer("-"*80, color
="bright"))
539 self
.logger
.info(colorer("Finalized SoC:", color
="cyan"))
540 self
.logger
.info(colorer("-"*80, color
="bright"))
541 self
.logger
.info(self
.bus
)
542 self
.logger
.info(self
.csr
)
543 self
.logger
.info(self
.irq
)
544 self
.logger
.info(colorer("-"*80, color
="bright"))
546 # SoC Bus Interconnect ---------------------------------------------------------------------
547 bus_masters
= self
.bus
.masters
.values()
548 bus_slaves
= [(self
.bus
.regions
[n
].decoder(), s
) for n
, s
in self
.bus
.slaves
.items()]
549 if len(bus_masters
) and len(bus_slaves
):
550 self
.submodules
.bus_interconnect
= wishbone
.InterconnectShared(
551 masters
= bus_masters
,
554 timeout_cycles
= self
.bus
.timeout
)
558 # Test (FIXME: move to litex/text and improve) -----------------------------------------------------
560 if __name__
== "__main__":
561 bus
= SoCBusHandler("wishbone", reserved_regions
={
562 "rom": SoCRegion(origin
=0x00000100, size
=1024),
563 "ram": SoCRegion(size
=512),
566 bus
.add_master("cpu", None)
567 bus
.add_slave("rom", None, SoCRegion(size
=1024))
568 bus
.add_slave("ram", None, SoCRegion(size
=1024))
571 csr
= SoCCSRHandler(reserved_csrs
={"ctrl": 0, "uart": 1})
579 irq
= SoCIRQHandler(reserved_irqs
={"uart": 1})