litex/soc/integration/soc_zynq.py

   1 # This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
   2 # License: BSD
   3
   4 import os
   5
   6 from migen import *
   7
   8 from litex.build.generic_platform import tools
   9 from litex.soc.integration.soc_core import *
  10 from litex.soc.integration.cpu_interface import get_csr_header
  11 from litex.soc.interconnect import wishbone
  12 from litex.soc.interconnect import axi
  13
  14 # Record layouts -----------------------------------------------------------------------------------
  15
  16 def axi_fifo_ctrl_layout():
  17     return [
  18         ("racount",         3, DIR_M_TO_S),
  19         ("rcount",          8, DIR_M_TO_S),
  20         ("rdissuecapen",    1, DIR_S_TO_M),
  21         ("wacount",         6, DIR_M_TO_S),
  22         ("wcount",          8, DIR_M_TO_S),
  23         ("wrissuecapen",    1, DIR_S_TO_M),
  24     ]
  25
  26 # SoC Zync -----------------------------------------------------------------------------------------
  27
  28 class SoCZynq(SoCCore):
  29     SoCCore.mem_map["csr"] = 0x00000000
  30     def __init__(self, platform, clk_freq, ps7_name, **kwargs):
  31         self.ps7_name = ps7_name
  32         SoCCore.__init__(self, platform, clk_freq, cpu_type=None, shadow_base=0x00000000, **kwargs)
  33
  34         # PS7 (Minimal) ----------------------------------------------------------------------------
  35         ps7_ddram_pads = platform.request("ps7_ddram")
  36         self.ps7_params = dict(
  37             # clk/rst
  38             io_PS_CLK=platform.request("ps7_clk"),
  39             io_PS_PORB=platform.request("ps7_porb"),
  40             io_PS_SRSTB=platform.request("ps7_srstb"),
  41
  42             # mio
  43             io_MIO=platform.request("ps7_mio"),
  44
  45             # ddram
  46             io_DDR_Addr=ps7_ddram_pads.addr,
  47             io_DDR_BankAddr=ps7_ddram_pads.ba,
  48             io_DDR_CAS_n=ps7_ddram_pads.cas_n,
  49             io_DDR_Clk_n=ps7_ddram_pads.ck_n,
  50             io_DDR_Clk=ps7_ddram_pads.ck_p,
  51             io_DDR_CKE=ps7_ddram_pads.cke,
  52             io_DDR_CS_n=ps7_ddram_pads.cs_n,
  53             io_DDR_DM=ps7_ddram_pads.dm,
  54             io_DDR_DQ=ps7_ddram_pads.dq,
  55             io_DDR_DQS_n=ps7_ddram_pads.dqs_n,
  56             io_DDR_DQS=ps7_ddram_pads.dqs_p,
  57             io_DDR_ODT=ps7_ddram_pads.odt,
  58             io_DDR_RAS_n=ps7_ddram_pads.ras_n,
  59             io_DDR_DRSTB=ps7_ddram_pads.reset_n,
  60             io_DDR_WEB=ps7_ddram_pads.we_n,
  61             io_DDR_VRN=ps7_ddram_pads.vrn,
  62             io_DDR_VRP=ps7_ddram_pads.vrp,
  63
  64             # ethernet
  65             i_ENET0_MDIO_I=0,
  66
  67             # sdio0
  68             i_SDIO0_WP=0,
  69
  70             # usb0
  71             i_USB0_VBUS_PWRFAULT=0,
  72
  73             # fabric clk
  74             o_FCLK_CLK0=ClockSignal("sys"),
  75
  76             # axi gp0 clk
  77             i_M_AXI_GP0_ACLK=ClockSignal("sys"),
  78         )
  79         platform.add_ip(os.path.join("ip", ps7_name + ".xci"))
  80
  81     # GP0 ------------------------------------------------------------------------------------------
  82
  83     def add_gp0(self):
  84         self.axi_gp0 = axi_gp0 = axi.AXIInterface(data_width=32, address_width=32, id_width=12)
  85         self.ps7_params.update(
  86             # axi gp0 aw
  87             o_M_AXI_GP0_AWVALID=axi_gp0.aw.valid,
  88             i_M_AXI_GP0_AWREADY=axi_gp0.aw.ready,
  89             o_M_AXI_GP0_AWADDR=axi_gp0.aw.addr,
  90             o_M_AXI_GP0_AWBURST=axi_gp0.aw.burst,
  91             o_M_AXI_GP0_AWLEN=axi_gp0.aw.len,
  92             o_M_AXI_GP0_AWSIZE=axi_gp0.aw.size,
  93             o_M_AXI_GP0_AWID=axi_gp0.aw.id,
  94             o_M_AXI_GP0_AWLOCK=axi_gp0.aw.lock,
  95             o_M_AXI_GP0_AWPROT=axi_gp0.aw.prot,
  96             o_M_AXI_GP0_AWCACHE=axi_gp0.aw.cache,
  97             o_M_AXI_GP0_AWQOS=axi_gp0.aw.qos,
  98
  99             # axi gp0 w
 100             o_M_AXI_GP0_WVALID=axi_gp0.w.valid,
 101             o_M_AXI_GP0_WLAST=axi_gp0.w.last,
 102             i_M_AXI_GP0_WREADY=axi_gp0.w.ready,
 103             o_M_AXI_GP0_WID=axi_gp0.w.id,
 104             o_M_AXI_GP0_WDATA=axi_gp0.w.data,
 105             o_M_AXI_GP0_WSTRB=axi_gp0.w.strb,
 106
 107             # axi gp0 b
 108             i_M_AXI_GP0_BVALID=axi_gp0.b.valid,
 109             o_M_AXI_GP0_BREADY=axi_gp0.b.ready,
 110             i_M_AXI_GP0_BID=axi_gp0.b.id,
 111             i_M_AXI_GP0_BRESP=axi_gp0.b.resp,
 112
 113             # axi gp0 ar
 114             o_M_AXI_GP0_ARVALID=axi_gp0.ar.valid,
 115             i_M_AXI_GP0_ARREADY=axi_gp0.ar.ready,
 116             o_M_AXI_GP0_ARADDR=axi_gp0.ar.addr,
 117             o_M_AXI_GP0_ARBURST=axi_gp0.ar.burst,
 118             o_M_AXI_GP0_ARLEN=axi_gp0.ar.len,
 119             o_M_AXI_GP0_ARID=axi_gp0.ar.id,
 120             o_M_AXI_GP0_ARLOCK=axi_gp0.ar.lock,
 121             o_M_AXI_GP0_ARSIZE=axi_gp0.ar.size,
 122             o_M_AXI_GP0_ARPROT=axi_gp0.ar.prot,
 123             o_M_AXI_GP0_ARCACHE=axi_gp0.ar.cache,
 124             o_M_AXI_GP0_ARQOS=axi_gp0.ar.qos,
 125
 126             # axi gp0 r
 127             i_M_AXI_GP0_RVALID=axi_gp0.r.valid,
 128             o_M_AXI_GP0_RREADY=axi_gp0.r.ready,
 129             i_M_AXI_GP0_RLAST=axi_gp0.r.last,
 130             i_M_AXI_GP0_RID=axi_gp0.r.id,
 131             i_M_AXI_GP0_RRESP=axi_gp0.r.resp,
 132             i_M_AXI_GP0_RDATA=axi_gp0.r.data,
 133         )
 134
 135     # HP0 ------------------------------------------------------------------------------------------
 136
 137     def add_hp0(self):
 138         self.axi_hp0 = axi_hp0 = axi.AXIInterface(data_width=64, address_width=32, id_width=6)
 139         self.axi_hp0_fifo_ctrl = axi_hp0_fifo_ctrl = Record(axi_fifo_ctrl_layout())
 140         self.ps7_params.update(
 141             # axi hp0 aw
 142             i_S_AXI_HP0_AWVALID=axi_hp0.aw.valid,
 143             o_S_AXI_HP0_AWREADY=axi_hp0.aw.ready,
 144             i_S_AXI_HP0_AWADDR=axi_hp0.aw.addr,
 145             i_S_AXI_HP0_AWBURST=axi_hp0.aw.burst,
 146             i_S_AXI_HP0_AWLEN=axi_hp0.aw.len,
 147             i_S_AXI_HP0_AWSIZE=axi_hp0.aw.size,
 148             i_S_AXI_HP0_AWID=axi_hp0.aw.id,
 149             i_S_AXI_HP0_AWLOCK=axi_hp0.aw.lock,
 150             i_S_AXI_HP0_AWPROT=axi_hp0.aw.prot,
 151             i_S_AXI_HP0_AWCACHE=axi_hp0.aw.cache,
 152             i_S_AXI_HP0_AWQOS=axi_hp0.aw.qos,
 153
 154             # axi hp0 w
 155             i_S_AXI_HP0_WVALID=axi_hp0.w.valid,
 156             i_S_AXI_HP0_WLAST=axi_hp0.w.last,
 157             o_S_AXI_HP0_WREADY=axi_hp0.w.ready,
 158             i_S_AXI_HP0_WID=axi_hp0.w.id,
 159             i_S_AXI_HP0_WDATA=axi_hp0.w.data,
 160             i_S_AXI_HP0_WSTRB=axi_hp0.w.strb,
 161
 162             # axi hp0 b
 163             o_S_AXI_HP0_BVALID=axi_hp0.b.valid,
 164             i_S_AXI_HP0_BREADY=axi_hp0.b.ready,
 165             o_S_AXI_HP0_BID=axi_hp0.b.id,
 166             o_S_AXI_HP0_BRESP=axi_hp0.b.resp,
 167
 168             # axi hp0 ar
 169             i_S_AXI_HP0_ARVALID=axi_hp0.ar.valid,
 170             o_S_AXI_HP0_ARREADY=axi_hp0.ar.ready,
 171             i_S_AXI_HP0_ARADDR=axi_hp0.ar.addr,
 172             i_S_AXI_HP0_ARBURST=axi_hp0.ar.burst,
 173             i_S_AXI_HP0_ARLEN=axi_hp0.ar.len,
 174             i_S_AXI_HP0_ARID=axi_hp0.ar.id,
 175             i_S_AXI_HP0_ARLOCK=axi_hp0.ar.lock,
 176             i_S_AXI_HP0_ARSIZE=axi_hp0.ar.size,
 177             i_S_AXI_HP0_ARPROT=axi_hp0.ar.prot,
 178             i_S_AXI_HP0_ARCACHE=axi_hp0.ar.cache,
 179             i_S_AXI_HP0_ARQOS=axi_hp0.ar.qos,
 180
 181             # axi hp0 r
 182             o_S_AXI_HP0_RVALID=axi_hp0.r.valid,
 183             i_S_AXI_HP0_RREADY=axi_hp0.r.ready,
 184             o_S_AXI_HP0_RLAST=axi_hp0.r.last,
 185             o_S_AXI_HP0_RID=axi_hp0.r.id,
 186             o_S_AXI_HP0_RRESP=axi_hp0.r.resp,
 187             o_S_AXI_HP0_RDATA=axi_hp0.r.data,
 188
 189             # axi hp0 fifo ctrl
 190             o_S_AXI_HP0_RACOUNT=axi_hp0_fifo_ctrl.racount,
 191             o_S_AXI_HP0_RCOUNT=axi_hp0_fifo_ctrl.rcount,
 192             i_S_AXI_HP0_RDISSUECAP1_EN=axi_hp0_fifo_ctrl.rdissuecapen,
 193             o_S_AXI_HP0_WACOUNT=axi_hp0_fifo_ctrl.wacount,
 194             o_S_AXI_HP0_WCOUNT=axi_hp0_fifo_ctrl.wcount,
 195             i_S_AXI_HP0_WRISSUECAP1_EN=axi_hp0_fifo_ctrl.wrissuecapen
 196         )
 197
 198     def add_axi_to_wishbone(self, axi_port, base_address=0x43c00000):
 199         wb = wishbone.Interface()
 200         axi2wishbone = axi.AXI2Wishbone(axi_port, wb, base_address)
 201         self.submodules += axi2wishbone
 202         self.add_wb_master(wb)
 203
 204     def do_finalize(self):
 205         SoCCore.do_finalize(self)
 206         self.specials += Instance(self.ps7_name, **self.ps7_params)
 207
 208     def generate_software_header(self, filename):
 209         csr_header = get_csr_header(self.get_csr_regions(),
 210                                     self.get_constants(),
 211                                     with_access_functions=False)
 212         tools.write_to_file(filename, csr_header)