litex/soc/interconnect/wishbone2csr.py

   1 from litex.gen import *
   2 from litex.gen.genlib.misc import timeline
   3
   4 from litex.soc.interconnect import csr_bus, wishbone
   5
   6
   7 class WB2CSR(Module):
   8     def __init__(self, bus_wishbone=None, bus_csr=None):
   9         if bus_wishbone is None:
  10             bus_wishbone = wishbone.Interface()
  11         self.wishbone = bus_wishbone
  12         if bus_csr is None:
  13             bus_csr = csr_bus.Interface()
  14         self.csr = bus_csr
  15
  16         ###
  17
  18         self.sync += [
  19             self.csr.we.eq(0),
  20             self.csr.dat_w.eq(self.wishbone.dat_w),
  21             self.csr.adr.eq(self.wishbone.adr),
  22             self.wishbone.dat_r.eq(self.csr.dat_r)
  23         ]
  24         self.sync += timeline(self.wishbone.cyc & self.wishbone.stb, [
  25             (1, [self.csr.we.eq(self.wishbone.we)]),
  26             (2, [self.wishbone.ack.eq(1)]),
  27             (3, [self.wishbone.ack.eq(0)])
  28         ])