litex/soc/misoc/cores/lasmicon/perf.py

   1 from migen import *
   2
   3 from misoc.interconnect.csr import *
   4
   5
   6 class Bandwidth(Module, AutoCSR):
   7     def __init__(self, cmd, data_width, period_bits=24):
   8         self._update = CSR()
   9         self._nreads = CSRStatus(period_bits)
  10         self._nwrites = CSRStatus(period_bits)
  11         self._data_width = CSRStatus(bits_for(data_width), reset=data_width)
  12
  13         ###
  14
  15         cmd_stb = Signal()
  16         cmd_ack = Signal()
  17         cmd_is_read = Signal()
  18         cmd_is_write = Signal()
  19         self.sync += [
  20             cmd_stb.eq(cmd.stb),
  21             cmd_ack.eq(cmd.ack),
  22             cmd_is_read.eq(cmd.is_read),
  23             cmd_is_write.eq(cmd.is_write)
  24         ]
  25
  26         counter = Signal(period_bits)
  27         period = Signal()
  28         nreads = Signal(period_bits)
  29         nwrites = Signal(period_bits)
  30         nreads_r = Signal(period_bits)
  31         nwrites_r = Signal(period_bits)
  32         self.sync += [
  33             Cat(counter, period).eq(counter + 1),
  34             If(period,
  35                 nreads_r.eq(nreads),
  36                 nwrites_r.eq(nwrites),
  37                 nreads.eq(0),
  38                 nwrites.eq(0)
  39             ).Elif(cmd_stb & cmd_ack,
  40                 If(cmd_is_read, nreads.eq(nreads + 1)),
  41                 If(cmd_is_write, nwrites.eq(nwrites + 1)),
  42             ),
  43             If(self._update.re,
  44                 self._nreads.status.eq(nreads_r),
  45                 self._nwrites.status.eq(nwrites_r)
  46             )
  47         ]