3 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
10 from litex
.build
import tools
14 print("usage: litex_read_verilog verilog_file [module]")
17 verilog_file
= sys
.argv
[1]
18 json_file
= verilog_file
+ ".json"
19 module
= None if len(sys
.argv
) < 3 else sys
.argv
[2]
21 # use yosys to convert verilog to json
22 yosys_v2j
= "\n".join([
23 "read_verilog -sv {}".format(verilog_file
),
24 "write_json {}.json".format(verilog_file
)
26 tools
.write_to_file("yosys_v2j.ys", yosys_v2j
)
27 os
.system("yosys -q yosys_v2j.ys")
29 # load json and convert to migen module
30 f
= open(json_file
, "r")
33 # create list of modules
34 modules
= [module
] if module
is not None else j
["modules"].keys()
36 # create migen definitions
37 for module
in modules
:
39 migen_def
.append("class {}(Module):".format(module
))
40 migen_def
.append(" "*4 + "def __init__(self):")
41 for name
, info
in j
["modules"][module
]["ports"].items():
42 length
= "" if len(info
["bits"]) == 1 else len(info
["bits"])
43 migen_def
.append(" " * 8 + "self.{} = Signal({})".format(name
, length
))
45 migen_def
.append(" "*8 + "# # #")
47 migen_def
.append(" "*8 + "self.specials += Instance(\"{}\",".format(module
))
48 for name
, info
in j
["modules"][module
]["ports"].items():
54 migen_def
.append(" "*12 + "{}_{}=self.{},".format(io_prefix
, name
, name
))
55 migen_def
.append(" "*8 + ")")
57 print("\n".join(migen_def
))
59 # keep things clean after us
60 os
.system("rm yosys_v2j.ys")
61 os
.system("rm " + json_file
)
64 if __name__
== "__main__":