make.py

   1 #!/usr/bin/env python3
   2
   3 import sys, os, argparse, subprocess, struct, importlib
   4
   5 from mibuild.tools import write_to_file
   6 from migen.util.misc import autotype
   7 from migen.fhdl import verilog, edif
   8 from migen.fhdl.structure import _Fragment
   9 from mibuild import tools
  10 from mibuild.xilinx_common import *
  11
  12 from misoclib.gensoc import cpuif
  13
  14 from liteeth.common import *
  15
  16 def _import(default, name):
  17         return importlib.import_module(default + "." + name)
  18
  19 def _get_args():
  20         parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
  21                 description="""\
  22 LiteEth - based on Migen.
  23
  24 This program builds and/or loads LiteEth components.
  25 One or several actions can be specified:
  26
  27 clean           delete previous build(s).
  28 build-rtl       build verilog rtl.
  29 build-bitstream build-bitstream build FPGA bitstream.
  30 build-csr-csv   save CSR map into CSV file.
  31
  32 load-bitstream  load bitstream into volatile storage.
  33
  34 all             clean, build-csr-csv, build-bitstream, load-bitstream.
  35 """)
  36
  37         parser.add_argument("-t", "--target", default="udp", help="Core type to build")
  38         parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build")
  39         parser.add_argument("-p", "--platform", default=None, help="platform to build for")
  40         parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
  41         parser.add_argument("-Op", "--platform-option", default=[("programmer", "vivado")], nargs=2, action="append", help="set platform-specific option")
  42         parser.add_argument("--csr_csv", default="./test/csr.csv", help="CSV file to save the CSR map into")
  43
  44         parser.add_argument("action", nargs="+", help="specify an action")
  45
  46         return parser.parse_args()
  47
  48 # Note: misoclib need to be installed as a python library
  49
  50 if __name__ == "__main__":
  51         args = _get_args()
  52
  53         # create top-level Core object
  54         target_module = _import("targets", args.target)
  55         if args.sub_target:
  56                 top_class = getattr(target_module, args.sub_target)
  57         else:
  58                 top_class = target_module.default_subtarget
  59
  60         if args.platform is None:
  61                 platform_name = top_class.default_platform
  62         else:
  63                 platform_name = args.platform
  64         platform_module = _import("platforms", platform_name)
  65         platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
  66         platform = platform_module.Platform(**platform_kwargs)
  67
  68         build_name = top_class.__name__.lower() +  "-" + platform_name
  69         top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
  70         soc = top_class(platform, **top_kwargs)
  71         soc.finalize()
  72
  73         # decode actions
  74         action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"]
  75         actions = {k: False for k in action_list}
  76         for action in args.action:
  77                 if action in actions:
  78                         actions[action] = True
  79                 else:
  80                         print("Unknown action: "+action+". Valid actions are:")
  81                         for a in action_list:
  82                                 print("  "+a)
  83                         sys.exit(1)
  84
  85         print("""
  86          __   _ __      ______  __
  87         / /  (_) /____ / __/ /_/ /
  88        / /__/ / __/ -_) _// __/ _ \\
  89       /____/_/\__/\__/___/\__/_//_/
  90
  91      A small footprint and configurable
  92               Ethernet core
  93
  94 ====== Building options: ======
  95 System Clk: {} MHz
  96 ===============================""".format(
  97         soc.clk_freq/1000000
  98         )
  99 )
 100
 101         # dependencies
 102         if actions["all"]:
 103                 actions["build-csr-csv"] = True
 104                 actions["build-bitstream"] = True
 105                 actions["load-bitstream"] = True
 106
 107         if actions["build-bitstream"]:
 108                 actions["build-csr-csv"] = True
 109                 actions["build-bitstream"] = True
 110                 actions["load-bitstream"] = True
 111
 112         if actions["clean"]:
 113                 subprocess.call(["rm", "-rf", "build/*"])
 114
 115         if actions["build-csr-csv"]:
 116                 csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
 117                 write_to_file(args.csr_csv, csr_csv)
 118
 119         if actions["build-bitstream"]:
 120                 platform.build(soc, build_name=build_name)
 121
 122         if actions["load-bitstream"]:
 123                 prog = platform.create_programmer()
 124                 prog.load_bitstream("build/" + build_name + platform.bitstream_ext)