3 import sys
, os
, argparse
, subprocess
, struct
, importlib
5 from mibuild
.tools
import write_to_file
6 from migen
.util
.misc
import autotype
7 from migen
.fhdl
import verilog
, edif
8 from migen
.fhdl
.structure
import _Fragment
9 from mibuild
import tools
10 from mibuild
.xilinx_common
import *
12 from misoclib
.gensoc
import cpuif
14 from litesata
.common
import *
16 def _import(default
, name
):
17 return importlib
.import_module(default
+ "." + name
)
20 parser
= argparse
.ArgumentParser(formatter_class
=argparse
.RawDescriptionHelpFormatter
,
22 LiteScope - based on Migen.
24 This program builds and/or loads LiteSATA components.
25 One or several actions can be specified:
27 clean delete previous build(s).
28 build-rtl build verilog rtl.
29 build-bitstream build-bitstream build FPGA bitstream.
30 build-csr-csv save CSR map into CSV file.
32 load-bitstream load bitstream into volatile storage.
34 all clean, build-csr-csv, build-bitstream, load-bitstream.
37 parser
.add_argument("-t", "--target", default
="simple", help="Core type to build")
38 parser
.add_argument("-s", "--sub-target", default
="", help="variant of the Core type to build")
39 parser
.add_argument("-p", "--platform", default
=None, help="platform to build for")
40 parser
.add_argument("-Ot", "--target-option", default
=[], nargs
=2, action
="append", help="set target-specific option")
41 parser
.add_argument("-Op", "--platform-option", default
=[], nargs
=2, action
="append", help="set platform-specific option")
42 parser
.add_argument("--csr_csv", default
="./test/csr.csv", help="CSV file to save the CSR map into")
44 parser
.add_argument("action", nargs
="+", help="specify an action")
46 return parser
.parse_args()
48 # Note: misoclib need to be installed as a python library
50 if __name__
== "__main__":
53 # create top-level Core object
54 target_module
= _import("targets", args
.target
)
56 top_class
= getattr(target_module
, args
.sub_target
)
58 top_class
= target_module
.default_subtarget
60 if args
.platform
is None:
61 platform_name
= top_class
.default_platform
63 platform_name
= args
.platform
64 platform_module
= _import("mibuild.platforms", platform_name
)
65 platform_kwargs
= dict((k
, autotype(v
)) for k
, v
in args
.platform_option
)
66 platform
= platform_module
.Platform(**platform_kwargs
)
68 build_name
= top_class
.__name
__.lower() + "-" + platform_name
69 top_kwargs
= dict((k
, autotype(v
)) for k
, v
in args
.target_option
)
70 soc
= top_class(platform
, **top_kwargs
)
74 action_list
= ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"]
75 actions
= {k
: False for k
in action_list
}
76 for action
in args
.action
:
78 actions
[action
] = True
80 print("Unknown action: "+action
+". Valid actions are:")
87 / / (_) /____ / __/______ ___ ___
88 / /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_)
89 /____/_/\__/\__/___/\__/\___/ .__/\__/
92 A small footprint and configurable embedded FPGA
95 ====== Building options: ======
96 ===============================""".format()
101 actions
["clean"] = True
102 actions
["build-csr-csv"] = True
103 actions
["build-bitstream"] = True
104 actions
["load-bitstream"] = True
106 if actions
["build-bitstream"]:
107 actions
["clean"] = True
108 actions
["build-csr-csv"] = True
109 actions
["build-bitstream"] = True
110 actions
["load-bitstream"] = True
113 subprocess
.call(["rm", "-rf", "build/*"])
115 if actions
["build-csr-csv"]:
116 csr_csv
= cpuif
.get_csr_csv(soc
.cpu_csr_regions
)
117 write_to_file(args
.csr_csv
, csr_csv
)
119 if actions
["build-bitstream"]:
120 platform
.build(soc
, build_name
=build_name
)
122 if actions
["load-bitstream"]:
123 prog
= platform
.create_programmer()
124 prog
.load_bitstream("build/" + build_name
+ platform
.bitstream_ext
)