make.py

   1 #!/usr/bin/env python3
   2
   3 import argparse, importlib, subprocess
   4
   5 from mibuild.tools import write_to_file
   6
   7 from misoclib.gensoc import cpuif
   8 from misoclib.s6ddrphy import initsequence
   9 import jtag
  10
  11 def _get_args():
  12         parser = argparse.ArgumentParser(description="MiSoC - a high performance SoC based on Migen.")
  13
  14         parser.add_argument("-p", "--platform", default="mixxeo", help="platform to build for")
  15         parser.add_argument("-t", "--target", default="mlabs_video", help="SoC type to build")
  16         parser.add_argument("-s", "--sub-target", default="", help="variant of the SoC type to build")
  17
  18         parser.add_argument("-B", "--no-bitstream", default=False, action="store_true", help="do not build bitstream file")
  19         parser.add_argument("-H", "--no-header", default=False, action="store_true", help="do not build C header files with CSR/IRQ/SDRAM_PHY definitions")
  20         parser.add_argument("-c", "--csr-csv", default="", help="save CSR map into CSV file")
  21
  22         parser.add_argument("-l", "--load", default=False, action="store_true", help="load bitstream to FPGA volatile memory")
  23         parser.add_argument("-f", "--flash", default=False, action="store_true", help="load bitstream to flash")
  24
  25         return parser.parse_args()
  26
  27 def main():
  28         args = _get_args()
  29
  30         platform_module = importlib.import_module("mibuild.platforms." + args.platform)
  31         target_module = importlib.import_module("targets." + args.target)
  32         platform = platform_module.Platform()
  33         if args.sub_target:
  34                 top_class = getattr(target_module, args.sub_target)
  35         else:
  36                 top_class = target_module.get_default_subtarget(platform)
  37         build_name = top_class.__name__.lower() + "-" + args.platform
  38         soc = top_class(platform)
  39
  40         if not args.no_bitstream:
  41                 platform.build(soc, build_name=build_name)
  42                 subprocess.call(["tools/byteswap",
  43                         "build/" + build_name + ".bin",
  44                         "build/" + build_name + ".fpg"])
  45         else:
  46                 soc.finalize()
  47         if not args.no_header:
  48                 boilerplate = """/*
  49  * Platform: {}
  50  * Target: {}
  51  * Subtarget: {}
  52  */
  53
  54 """.format(args.platform, args.target, top_class.__name__)
  55                 csr_header = cpuif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
  56                 write_to_file("software/include/hw/csr.h", boilerplate + csr_header)
  57                 sdram_phy_header = initsequence.get_sdram_phy_header(soc.ddrphy)
  58                 write_to_file("software/include/hw/sdram_phy.h", boilerplate + sdram_phy_header)
  59         if args.csr_csv:
  60                 csr_csv = cpuif.get_csr_csv(soc.csr_base, soc.csrbankarray)
  61                 write_to_file(args.csr_csv, csr_csv)
  62
  63         if args.load:
  64                 jtag.load("build/" + build_name + ".bit")
  65         if args.flash:
  66                 jtag.flash("build/" + build_name + ".fpg")
  67
  68 if __name__ == "__main__":
  69         main()