mibuild/mibuild/platforms/lx9_microboard.py

   1 from mibuild.generic_platform import *
   2 from mibuild.xilinx_ise import XilinxISEPlatform, CRG_SE
   3
   4 _io = [
   5                 ("user_btn", 0, Pins("V4"), IOStandard("LVCMOS33"),
   6                         Misc("PULLDOWN"), Misc("TIG")),
   7
   8                 ("user_led", 0, Pins("P4"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")),
   9                 ("user_led", 1, Pins("L6"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")),
  10                 ("user_led", 2, Pins("F5"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")),
  11                 ("user_led", 3, Pins("C2"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")),
  12
  13                 ("user_dip", 0, Pins("B3"), Misc("PULLDOWN"), IOStandard("LVCMOS33")),
  14                 ("user_dip", 1, Pins("A3"), Misc("PULLDOWN"), IOStandard("LVCMOS33")),
  15                 ("user_dip", 2, Pins("B4"), Misc("PULLDOWN"), IOStandard("LVCMOS33")),
  16                 ("user_dip", 3, Pins("A4"), Misc("PULLDOWN"), IOStandard("LVCMOS33")),
  17
  18                 # TI CDCE913 programmable triple-output PLL
  19                 ("clk_y1", 0, Pins("V10"), IOStandard("LVCMOS33")), # default: 40 MHz
  20                 ("clk_y2", 0, Pins("K15"), IOStandard("LVCMOS33")), # default: 66 2/3 MHz
  21                 ("clk_y3", 0, Pins("C10"), IOStandard("LVCMOS33")), # default: 100 MHz
  22
  23                 # Maxim DS1088LU oscillator, not populated
  24                 ("clk_backup", 0, Pins("R8"), IOStandard("LVCMOS33")),
  25
  26                 # TI CDCE913 PLL I2C control
  27                 ("pll", 0,
  28                         Subsignal("scl", Pins("P12")),
  29                         Subsignal("sda", Pins("U13")),
  30                         Misc("PULLUP"),
  31                         IOStandard("LVCMOS33")),
  32
  33                 # Micron N25Q128 SPI Flash
  34                 ("spiflash", 0,
  35                         Subsignal("clk", Pins("R15")),
  36                         Subsignal("cs_n", Pins("V3")),
  37                         Subsignal("dq", Pins("T13 R13 T14 V14")),
  38                         IOStandard("LVCMOS33")),
  39
  40                 # PMOD extension connectors
  41                 ("pmod", 0,
  42                         Subsignal("d", Pins("F15 F16 C17 C18 F14 G14 D17 D18")),
  43                         IOStandard("LVCMOS33")),
  44                 ("pmod", 1,
  45                         Subsignal("d", Pins("H12 G13 E16 E18 K12 K13 F17 F18")),
  46                         IOStandard("LVCMOS33")),
  47
  48                 ("serial", 0,
  49                         Subsignal("tx", Pins("T7"), Misc("SLEW=SLOW")),
  50                         Subsignal("rx", Pins("R7"), Misc("PULLUP")),
  51                         IOStandard("LVCMOS33")),
  52
  53                 ("ddram_clock", 0,
  54                         Subsignal("p", Pins("G3")),
  55                         Subsignal("n", Pins("G1")),
  56                         IOStandard("MOBILE_DDR")), # actually DIFF_
  57
  58                 # Micron MT46H32M16LFBF-5 LPDDR
  59                 ("ddram", 0,
  60                         Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 "
  61                                 "D2 D1 F4 D3 G6")),
  62                         Subsignal("ba", Pins("F2 F1")),
  63                         Subsignal("dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 "
  64                                 "M3 M1 N2 N1 T2 T1 U2 U1")),
  65                         Subsignal("cke", Pins("H7")),
  66                         Subsignal("we_n", Pins("E3")),
  67                         Subsignal("cs_n", Pins("K6")), # NC!
  68                         Subsignal("cas_n", Pins("K5")),
  69                         Subsignal("ras_n", Pins("L5")),
  70                         Subsignal("dm", Pins("K3", "K4")),
  71                         Subsignal("dqs", Pins("L4", "P2")),
  72                         Subsignal("rzq", Pins("N4")),
  73                         IOStandard("MOBILE_DDR")),
  74
  75                 # Nat Semi DP83848J 10/100 Ethernet PHY
  76                 # pull-ups on rx_data set phy addr to 11110b
  77                 # and prevent isolate mode (addr 00000b)
  78                 ("eth_clocks", 0,
  79                         Subsignal("rx", Pins("L15")),
  80                         Subsignal("tx", Pins("H17")),
  81                         IOStandard("LVCMOS33")),
  82
  83                 ("eth", 0,
  84                         Subsignal("col", Pins("M18"), Misc("PULLDOWN")),
  85                         Subsignal("crs", Pins("N17"), Misc("PULLDOWN")),
  86                         Subsignal("mdc", Pins("M16")),
  87                         Subsignal("mdio", Pins("L18")),
  88                         Subsignal("rst_n", Pins("T18"), Misc("TIG")),
  89                         Subsignal("rx_data", Pins("T17 N16 N15 P18"), Misc("PULLUP")),
  90                         Subsignal("dv", Pins("P17")),
  91                         Subsignal("rx_er", Pins("N18")),
  92                         Subsignal("tx_data", Pins("K18 K17 J18 J16")),
  93                         Subsignal("tx_en", Pins("L17")),
  94                         Subsignal("tx_er", Pins("L16")), # NC!
  95                         IOStandard("LVCMOS33")),
  96                 ]
  97
  98
  99 class Platform(XilinxISEPlatform):
 100         def __init__(self):
 101                 XilinxISEPlatform.__init__(self, "xc6slx9-2csg324", _io,
 102                                 lambda p: CRG_SE(p, "clk_y3", "user_btn", 10.))
 103                 self.add_platform_command("""
 104 CONFIG VCCAUX = "3.3";
 105 """)
 106
 107         def do_finalize(self, fragment):
 108                 try:
 109                         eth_clocks = self.lookup_request("eth_clocks")
 110                         self.add_platform_command("""
 111 NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk";
 112 NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk";
 113 TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
 114 TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%;
 115 TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
 116 TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
 117 """, phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx)
 118                 except ContraintError:
 119                         pass