mibuild/platforms/mixxeo.py

   1 from mibuild.generic_platform import *
   2 from mibuild.crg import SimpleCRG
   3 from mibuild.xilinx.ise import XilinxISEPlatform
   4 from mibuild.xilinx.programmer import UrJTAG
   5
   6 _io = [
   7         ("user_led", 0, Pins("V5"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
   8
   9         ("clk50", 0, Pins("AB13"), IOStandard("LVCMOS33")),
  10
  11         # When executing softcore code in-place from the flash, we want
  12         # the flash reset to be released before the system reset.
  13         ("norflash_rst_n", 0, Pins("P22"), IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)),
  14         ("norflash", 0,
  15                 Subsignal("adr", Pins("L22 L20 K22 K21 J19 H20 F22",
  16                         "F21 K17 J17 E22 E20 H18 H19 F20",
  17                         "G19 C22 C20 D22 D21 F19 F18 D20 D19")),
  18                 Subsignal("d", Pins("AA20 U14 U13 AA6 AB6 W4 Y4 Y7",
  19                         "AA2 AB2 V15 AA18 AB18 Y13 AA12 AB12"), Misc("PULLDOWN")),
  20                 Subsignal("oe_n", Pins("M22")),
  21                 Subsignal("we_n", Pins("N20")),
  22                 Subsignal("ce_n", Pins("M21")),
  23                 IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)
  24         ),
  25
  26         ("serial", 0,
  27                 Subsignal("tx", Pins("L17"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")),
  28                 Subsignal("rx", Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLUP"))
  29         ),
  30
  31         ("ddram_clock", 0,
  32                 Subsignal("p", Pins("M3")),
  33                 Subsignal("n", Pins("L4")),
  34                 IOStandard("SSTL2_I")
  35         ),
  36         ("ddram", 0,
  37                 Subsignal("a", Pins("B1 B2 H8 J7 E4 D5 K7 F5 G6 C1 C3 D1 D2")),
  38                 Subsignal("ba", Pins("A2 E6")),
  39                 Subsignal("cs_n", Pins("F7")),
  40                 Subsignal("cke", Pins("G7")),
  41                 Subsignal("ras_n", Pins("E5")),
  42                 Subsignal("cas_n", Pins("C4")),
  43                 Subsignal("we_n", Pins("D3")),
  44                 Subsignal("dq", Pins("Y2 W3 W1 P8 P7 P6 P5 T4 T3",
  45                         "U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4",
  46                         "M5 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1")),
  47                 Subsignal("dm", Pins("E1 E3 F3 G4")),
  48                 Subsignal("dqs", Pins("F1 F2 H5 H6")),
  49                 IOStandard("SSTL2_I")
  50         ),
  51
  52         ("eth_clocks", 0,
  53                 Subsignal("phy", Pins("M20")),
  54                 Subsignal("rx", Pins("H22")),
  55                 Subsignal("tx", Pins("H21")),
  56                 IOStandard("LVCMOS33")
  57         ),
  58         ("eth", 0,
  59                 Subsignal("rst_n", Pins("R22")),
  60                 Subsignal("dv", Pins("V21")),
  61                 Subsignal("rx_er", Pins("V22")),
  62                 Subsignal("rx_data", Pins("U22 U20 T22 T21")),
  63                 Subsignal("tx_en", Pins("N19")),
  64                 Subsignal("tx_er", Pins("M19")),
  65                 Subsignal("tx_data", Pins("M16 L15 P19 P20")),
  66                 Subsignal("col", Pins("W20")),
  67                 Subsignal("crs", Pins("W22")),
  68                 IOStandard("LVCMOS33")
  69         ),
  70
  71         ("vga_out", 0,
  72                 Subsignal("clk", Pins("A10")),
  73                 Subsignal("r", Pins("C6 B6 A6 C7 A7 B8 A8 D9")),
  74                 Subsignal("g", Pins("C8 C9 A9 D7 D8 D10 C10 B10")),
  75                 Subsignal("b", Pins("D11 C12 B12 A12 C13 A13 D14 C14")),
  76                 Subsignal("hsync_n", Pins("A14")),
  77                 Subsignal("vsync_n", Pins("C15")),
  78                 Subsignal("psave_n", Pins("B14")),
  79                 IOStandard("LVCMOS33")
  80         ),
  81         ("dvi_out", 0,
  82                 Subsignal("clk_p", Pins("W12"), IOStandard("TMDS_33")),
  83                 Subsignal("clk_n", Pins("Y12"), IOStandard("TMDS_33")),
  84                 Subsignal("data0_p", Pins("Y16"), IOStandard("TMDS_33")),
  85                 Subsignal("data0_n", Pins("W15"), IOStandard("TMDS_33")),
  86                 Subsignal("data1_p", Pins("AA16"), IOStandard("TMDS_33")),
  87                 Subsignal("data1_n", Pins("AB16"), IOStandard("TMDS_33")),
  88                 Subsignal("data2_p", Pins("Y15"), IOStandard("TMDS_33")),
  89                 Subsignal("data2_n", Pins("AB15"), IOStandard("TMDS_33")),
  90         ),
  91
  92         ("mmc", 0,
  93                 Subsignal("clk", Pins("J3")),
  94                 Subsignal("cmd", Pins("K1")),
  95                 Subsignal("dat", Pins("J6 K6 N1 K5")),
  96                 IOStandard("LVCMOS33")
  97         ),
  98
  99         ("dvi_in", 0,
 100                 Subsignal("clk_p", Pins("K20"), IOStandard("TMDS_33")),
 101                 Subsignal("clk_n", Pins("K19"), IOStandard("TMDS_33")),
 102                 Subsignal("data0_p", Pins("B21"), IOStandard("TMDS_33")),
 103                 Subsignal("data0_n", Pins("B22"), IOStandard("TMDS_33")),
 104                 Subsignal("data1_p", Pins("A20"), IOStandard("TMDS_33")),
 105                 Subsignal("data1_n", Pins("A21"), IOStandard("TMDS_33")),
 106                 Subsignal("data2_p", Pins("K16"), IOStandard("TMDS_33")),
 107                 Subsignal("data2_n", Pins("J16"), IOStandard("TMDS_33")),
 108                 Subsignal("scl", Pins("G20"), IOStandard("LVCMOS33")),
 109                 Subsignal("sda", Pins("H16"), IOStandard("LVCMOS33")),
 110                 Subsignal("hpd_notif", Pins("G22"), IOStandard("LVCMOS33")),
 111                 Subsignal("hpd_en", Pins("G17"), IOStandard("LVCMOS33"))
 112         ),
 113         ("dvi_in", 1,
 114                 Subsignal("clk_p", Pins("C11"), IOStandard("TMDS_33")),
 115                 Subsignal("clk_n", Pins("A11"), IOStandard("TMDS_33")),
 116                 Subsignal("data0_p", Pins("B18"), IOStandard("TMDS_33")),
 117                 Subsignal("data0_n", Pins("A18"), IOStandard("TMDS_33")),
 118                 Subsignal("data1_p", Pins("C17"), IOStandard("TMDS_33")),
 119                 Subsignal("data1_n", Pins("A17"), IOStandard("TMDS_33")),
 120                 Subsignal("data2_p", Pins("E16"), IOStandard("TMDS_33")),
 121                 Subsignal("data2_n", Pins("D17"), IOStandard("TMDS_33")),
 122                 Subsignal("scl", Pins("F17"), IOStandard("LVCMOS33")),
 123                 Subsignal("sda", Pins("F16"), IOStandard("LVCMOS33")),
 124                 Subsignal("hpd_notif", Pins("G16"), IOStandard("LVCMOS33")),
 125                 Subsignal("hpd_en", Pins("B20"), IOStandard("LVCMOS33"))
 126         ),
 127         ("dvi_in", 2,
 128                 Subsignal("clk_p", Pins("Y11"), IOStandard("TMDS_33")),
 129                 Subsignal("clk_n", Pins("AB11"), IOStandard("TMDS_33")),
 130                 Subsignal("data0_p", Pins("V11"), IOStandard("TMDS_33")),
 131                 Subsignal("data0_n", Pins("W11"), IOStandard("TMDS_33")),
 132                 Subsignal("data1_p", Pins("AA10"), IOStandard("TMDS_33")),
 133                 Subsignal("data1_n", Pins("AB10"), IOStandard("TMDS_33")),
 134                 Subsignal("data2_p", Pins("R11"), IOStandard("TMDS_33")),
 135                 Subsignal("data2_n", Pins("T11"), IOStandard("TMDS_33")),
 136                 Subsignal("scl", Pins("C16"), IOStandard("LVCMOS33")),
 137                 Subsignal("sda", Pins("B16"), IOStandard("LVCMOS33")),
 138                 Subsignal("hpd_notif", Pins("D6"), IOStandard("LVCMOS33")),
 139                 Subsignal("hpd_en", Pins("A4"), IOStandard("LVCMOS33"))
 140         ),
 141         ("dvi_in", 3,
 142                 Subsignal("clk_p", Pins("J20"), IOStandard("TMDS_33")),
 143                 Subsignal("clk_n", Pins("J22"), IOStandard("TMDS_33")),
 144                 Subsignal("data0_p", Pins("P18"), IOStandard("TMDS_33")),
 145                 Subsignal("data0_n", Pins("R19"), IOStandard("TMDS_33")),
 146                 Subsignal("data1_p", Pins("P17"), IOStandard("TMDS_33")),
 147                 Subsignal("data1_n", Pins("N16"), IOStandard("TMDS_33")),
 148                 Subsignal("data2_p", Pins("M17"), IOStandard("TMDS_33")),
 149                 Subsignal("data2_n", Pins("M18"), IOStandard("TMDS_33")),
 150                 Subsignal("scl", Pins("P21"), IOStandard("LVCMOS33")),
 151                 Subsignal("sda", Pins("N22"), IOStandard("LVCMOS33")),
 152                 Subsignal("hpd_notif", Pins("H17"), IOStandard("LVCMOS33")),
 153                 Subsignal("hpd_en", Pins("C19"), IOStandard("LVCMOS33"))
 154         ),
 155 ]
 156
 157 class Platform(XilinxISEPlatform):
 158         identifier = 0x4D58
 159         default_clk_name = "clk50"
 160         default_clk_period = 20
 161         def __init__(self):
 162                 XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
 163                         lambda p: SimpleCRG(p, "clk50", None))
 164                 self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n")
 165
 166         def create_programmer(self):
 167                 return UrJTAG("fjmem-mixxeo.bit")
 168
 169         def do_finalize(self, fragment):
 170                 try:
 171                         self.add_period_constraint(self.lookup_request("clk50"), 20)
 172                 except ConstraintError:
 173                         pass
 174
 175                 try:
 176                         eth_clocks = self.lookup_request("eth_clocks")
 177                         self.add_period_constraint(eth_clocks.rx, 40)
 178                         self.add_period_constraint(eth_clocks.tx, 40)
 179                         self.add_platform_command("""
 180 TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns;
 181 TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns;
 182 """, phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx)
 183                 except ConstraintError:
 184                         pass
 185
 186                 for i in range(4):
 187                         try:
 188                                 self.add_period_constraint(self.lookup_request("dvi_in", i).clk_p, 12)
 189                         except ConstraintError:
 190                                 pass