migen/build/lattice/common.py

   1 from migen.fhdl.module import Module
   2 from migen.fhdl.specials import Instance
   3 from migen.genlib.io import *
   4 from migen.genlib.resetsync import AsyncResetSynchronizer
   5
   6
   7 class LatticeAsyncResetSynchronizerImpl(Module):
   8     def __init__(self, cd, async_reset):
   9         rst1 = Signal()
  10         self.specials += [
  11             Instance("FD1S3BX", i_D=0, i_PD=async_reset,
  12                 i_CK=cd.clk, o_Q=rst1),
  13             Instance("FD1S3BX", i_D=rst1, i_PD=async_reset,
  14                 i_CK=cd.clk, o_Q=cd.rst)
  15         ]
  16
  17
  18 class LatticeAsyncResetSynchronizer:
  19     @staticmethod
  20     def lower(dr):
  21         return LatticeAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
  22
  23
  24 class LatticeDDROutputImpl(Module):
  25     def __init__(self, i1, i2, o, clk):
  26         self.specials += Instance("ODDRXD1",
  27                 synthesis_directive="ODDRAPPS=\"SCLK_ALIGNED\"",
  28                 i_SCLK=clk,
  29                 i_DA=i1, i_DB=i2, o_Q=o,
  30         )
  31
  32
  33 class LatticeDDROutput:
  34     @staticmethod
  35     def lower(dr):
  36         return LatticeDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
  37
  38 lattice_special_overrides = {
  39     AsyncResetSynchronizer: LatticeAsyncResetSynchronizer,
  40     DDROutput: LatticeDDROutput
  41 }