1 # This file is Copyright (c) 2015 Matt O'Gorman <mog@rldn.net>
4 from migen
.build
.generic_platform
import *
5 from migen
.build
.xilinx
import XilinxPlatform
6 from migen
.build
.xilinx
.programmer
import XC3SProg
, FpgaProg
10 ("user_led", 0, Pins("P11"), IOStandard("LVCMOS33")),
11 ("user_led", 1, Pins("N9"), IOStandard("LVCMOS33")),
12 ("user_led", 2, Pins("M9"), IOStandard("LVCMOS33")),
13 ("user_led", 3, Pins("P9"), IOStandard("LVCMOS33")),
14 ("user_led", 4, Pins("T8"), IOStandard("LVCMOS33")),
15 ("user_led", 5, Pins("N8"), IOStandard("LVCMOS33")),
16 ("user_led", 6, Pins("P8"), IOStandard("LVCMOS33")),
17 ("user_led", 7, Pins("P7"), IOStandard("LVCMOS33")),
19 ("user_sw", 0, Pins("L1"), IOStandard("LVCMOS33"), Misc("PULLUP")),
20 ("user_sw", 1, Pins("L3"), IOStandard("LVCMOS33"), Misc("PULLUP")),
21 ("user_sw", 2, Pins("L4"), IOStandard("LVCMOS33"), Misc("PULLUP")),
22 ("user_sw", 3, Pins("L5"), IOStandard("LVCMOS33"), Misc("PULLUP")),
24 ("clk32", 0, Pins("J4"), IOStandard("LVCMOS33")),
25 ("clk50", 0, Pins("K3"), IOStandard("LVCMOS33")),
28 Subsignal("cs_n", Pins("T3"), IOStandard("LVCMOS33")),
29 Subsignal("clk", Pins("R11"), IOStandard("LVCMOS33")),
30 Subsignal("mosi", Pins("T10"), IOStandard("LVCMOS33")),
31 Subsignal("miso", Pins("P10"), IOStandard("LVCMOS33"))
35 Subsignal("cs_n", Pins("F6"), IOStandard("LVCMOS33")),
36 Subsignal("clk", Pins("G6"), IOStandard("LVCMOS33")),
37 Subsignal("mosi", Pins("H4"), IOStandard("LVCMOS33")),
38 Subsignal("miso", Pins("H5"), IOStandard("LVCMOS33"))
42 Subsignal("tx", Pins("N6"), IOStandard("LVCMOS33")), # FTDI D1
43 Subsignal("rx", Pins("M7"), IOStandard("LVCMOS33")) # FTDI D0
47 Subsignal("a0", Pins("B8"), IOStandard("LVCMOS33")),
48 Subsignal("a1", Pins("A8"), IOStandard("LVCMOS33"))
51 ("sdram_clock", 0, Pins("G16"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
53 Subsignal("a", Pins("T15 R16 P15 P16 N16 M15 M16 L16 K15 K16 R15 J16 H15")),
54 Subsignal("dq", Pins("T13 T12 R12 T9 R9 T7 R7 T6 F16 E15 E16 D16 B16 B15 C16 C15")),
55 Subsignal("we_n", Pins("R5")),
56 Subsignal("ras_n", Pins("R2")),
57 Subsignal("cas_n", Pins("T4")),
58 Subsignal("cs_n", Pins("R1")),
59 Subsignal("cke", Pins("H16")),
60 Subsignal("ba", Pins("R14 T14")),
61 Subsignal("dm", Pins("T5 F15")),
62 IOStandard("LVCMOS33"), Misc("SLEW=FAST")
66 Subsignal("data", Pins("M7 N6 M6 P5 N5 P4 P2 P1")),
67 Subsignal("rxf_n", Pins("N3")),
68 Subsignal("txe_n", Pins("N1")),
69 Subsignal("rd_n", Pins("M1")),
70 Subsignal("wr_n", Pins("M2")),
71 Subsignal("siwua", Pins("M3")),
72 IOStandard("LVCMOS33"), Drive(8), Misc("SLEW=FAST")
76 Subsignal("sck", Pins("L12")),
77 Subsignal("d3", Pins("K12")),
78 Subsignal("d", Pins("M10")),
79 Subsignal("d1", Pins("L10")),
80 Subsignal("d2", Pins("J11")),
81 Subsignal("cmd", Pins("K11")),
82 IOStandard("LVCMOS33")
86 Subsignal("clk_p", Pins("C9"), IOStandard("TMDS_33")),
87 Subsignal("clk_n", Pins("A9"), IOStandard("TMDS_33")),
88 Subsignal("data_p", Pins("C7 B6 B5"), IOStandard("TMDS_33")),
89 Subsignal("data_n", Pins("A7 A6 A5"), IOStandard("TMDS_33")),
90 Subsignal("scl", Pins("C1"), IOStandard("LVCMOS33")),
91 Subsignal("sda", Pins("B1"), IOStandard("LVCMOS33"))
95 Subsignal("clk_p", Pins("B14"), IOStandard("TMDS_33")),
96 Subsignal("clk_n", Pins("A14"), IOStandard("TMDS_33")),
97 Subsignal("data_p", Pins("C13 B12 C11"), IOStandard("TMDS_33")),
98 Subsignal("data_n", Pins("A13 A12 A11"), IOStandard("TMDS_33")),
103 ("A", "E7 C8 D8 E8 D9 A10 B10 C10 E10 F9 F10 D11"),
104 ("B", "E11 D14 D12 E12 E13 F13 F12 F14 G12 H14 J14"),
105 ("C", "J13 J12 K14 L14 L13 M14 M13 N14 M12 N12 P12 M11"),
106 ("D", "D6 C6 E6 C5"),
107 ("E", "D5 A4 G5 A3 B3 A2 B2 C3 C2 D3 D1 E3"),
108 ("F", "E2 E1 E4 F4 F5 G3 F3 G1 H3 H1 H2 J1")
112 class Platform(XilinxPlatform
):
113 default_clk_name
= "clk32"
114 default_clk_period
= 31.25
116 def __init__(self
, device
="xc6slx9", programmer
="xc3sprog"):
117 self
.programmer
= programmer
118 XilinxPlatform
.__init
__(self
, device
+"-3-ftg256", _io
, _connectors
)
120 def create_programmer(self
):
121 if self
.programmer
== "xc3sprog":
122 return XC3SProg("minispartan6", "bscan_spi_minispartan6.bit")
123 elif self
.programmer
== "fpgaprog":
126 raise ValueError("{} programmer is not supported".format(programmer
))