migen/build/platforms/sim.py

   1 from migen.build.generic_platform import *
   2 from migen.build.sim import SimPlatform
   3
   4
   5 class SimPins(Pins):
   6     def __init__(self, n):
   7         Pins.__init__(self, "s "*n)
   8
   9 _io = [
  10     ("sys_clk", 0, SimPins(1)),
  11     ("sys_rst", 0, SimPins(1)),
  12     ("serial", 0,
  13         Subsignal("source_stb", SimPins(1)),
  14         Subsignal("source_ack", SimPins(1)),
  15         Subsignal("source_data", SimPins(8)),
  16
  17         Subsignal("sink_stb", SimPins(1)),
  18         Subsignal("sink_ack", SimPins(1)),
  19         Subsignal("sink_data", SimPins(8)),
  20     ),
  21     ("eth_clocks", 0,
  22         Subsignal("none", SimPins(1)),
  23     ),
  24     ("eth", 0,
  25         Subsignal("source_stb", SimPins(1)),
  26         Subsignal("source_ack", SimPins(1)),
  27         Subsignal("source_data", SimPins(8)),
  28
  29         Subsignal("sink_stb", SimPins(1)),
  30         Subsignal("sink_ack", SimPins(1)),
  31         Subsignal("sink_data", SimPins(8)),
  32     ),
  33 ]
  34
  35
  36 class Platform(SimPlatform):
  37     is_sim = True
  38     default_clk_name = "sys_clk"
  39     default_clk_period = 1000  # on modern computers simulate at ~ 1MHz
  40
  41     def __init__(self):
  42         SimPlatform.__init__(self, "SIM", _io)
  43
  44     def do_finalize(self, fragment):
  45         pass