milkymist/cif.py

   1 from operator import itemgetter
   2 import re
   3
   4 from migen.fhdl.std import *
   5 from migen.bank.description import CSRStatus
   6
   7 def get_macros(filename):
   8         f = open(filename, "r")
   9         r = {}
  10         for line in f:
  11                 match = re.match("\w*#define\s+(\w+)\s+(.*)", line, re.IGNORECASE)
  12                 if match:
  13                         r[match.group(1)] = match.group(2)
  14         return r
  15
  16 def _get_rw_functions(reg_name, reg_base, size, read_only):
  17         r = ""
  18         if size > 8:
  19                 raise NotImplementedError("Register too large")
  20         elif size > 4:
  21                 ctype = "unsigned long long int"
  22         elif size > 2:
  23                 ctype = "unsigned int"
  24         elif size > 1:
  25                 ctype = "unsigned short int"
  26         else:
  27                 ctype = "unsigned char"
  28
  29         r += "static inline "+ctype+" "+reg_name+"_read(void) {\n"
  30         if size > 1:
  31                 r += "\t"+ctype+" r = MMPTR("+hex(reg_base)+");\n"
  32                 for byte in range(1, size):
  33                         r += "\tr <<= 8;\n\tr |= MMPTR("+hex(reg_base+4*byte)+");\n"
  34                 r += "\treturn r;\n}\n"
  35         else:
  36                 r += "\treturn MMPTR("+hex(reg_base)+");\n}\n"
  37
  38         if not read_only:
  39                 r += "static inline void "+reg_name+"_write("+ctype+" value) {\n"
  40                 for byte in range(size):
  41                         shift = (size-byte-1)*8
  42                         if shift:
  43                                 value_shifted = "value >> "+str(shift)
  44                         else:
  45                                 value_shifted = "value"
  46                         r += "\tMMPTR("+hex(reg_base+4*byte)+") = "+value_shifted+";\n"
  47                 r += "}\n"
  48         return r
  49
  50 def get_csr_header(csr_base, bank_array, interrupt_map):
  51         r = "#ifndef __HW_CSR_H\n#define __HW_CSR_H\n#include <hw/common.h>\n"
  52         for name, csrs, mapaddr, rmap in bank_array.banks:
  53                 r += "\n/* "+name+" */\n"
  54                 reg_base = csr_base + 0x800*mapaddr
  55                 r += "#define "+name.upper()+"_BASE "+hex(reg_base)+"\n"
  56                 for csr in csrs:
  57                         nr = (csr.size + 7)//8
  58                         r += _get_rw_functions(name + "_" + csr.name, reg_base, nr, isinstance(csr, CSRStatus))
  59                         reg_base += 4*nr
  60                 try:
  61                         interrupt_nr = interrupt_map[name]
  62                 except KeyError:
  63                         pass
  64                 else:
  65                         r += "#define "+name.upper()+"_INTERRUPT "+str(interrupt_nr)+"\n"
  66         r += "\n#endif\n"
  67         return r
  68
  69 def get_sdram_phy_header(sdram_phy):
  70                 if sdram_phy.phy_settings.type not in ["SDR", "DDR", "LPDDR", "DDR2"]:
  71                         raise NotImplementedError("The SDRAM PHY header generator only supports SDR, DDR, LPDDR and DDR2")
  72
  73                 r = "#ifndef __HW_SDRAM_PHY_H\n#define __HW_SDRAM_PHY_H\n"
  74                 r += "#include <hw/common.h>\n#include <hw/csr.h>\n#include <hw/flags.h>\n\n"
  75
  76                 r += "static void cdelay(int i);\n"
  77
  78                 #
  79                 # commands_px functions
  80                 #
  81                 for n in range(sdram_phy.phy_settings.nphases):
  82                         r += """
  83 static void command_p{n}(int cmd)
  84 {{
  85         dfii_pi{n}_command_write(cmd);
  86         dfii_pi{n}_command_issue_write(1);
  87 }}""".format(n=str(n))
  88                 r += "\n\n"
  89
  90                 #
  91                 # rd/wr access macros
  92                 #
  93                 r += """
  94 #define dfii_pird_address_write(X) dfii_pi{rdphase}_address_write(X)
  95 #define dfii_piwr_address_write(X) dfii_pi{wrphase}_address_write(X)
  96
  97 #define dfii_pird_baddress_write(X) dfii_pi{rdphase}_baddress_write(X)
  98 #define dfii_piwr_baddress_write(X) dfii_pi{wrphase}_baddress_write(X)
  99
 100 #define command_prd(X) command_p{rdphase}(X)
 101 #define command_pwr(X) command_p{wrphase}(X)
 102 """.format(rdphase=str(sdram_phy.phy_settings.rdphase), wrphase=str(sdram_phy.phy_settings.wrphase))
 103                 r +="\n"
 104
 105                 #
 106                 # init sequence
 107                 #
 108                 cmds = {
 109                         "PRECHARGE_ALL" : "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
 110                         "MODE_REGISTER" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
 111                         "AUTO_REFRESH"  : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
 112                         "CKE"           : "DFII_CONTROL_CKE"
 113                 }
 114
 115                 def gen_cmd(comment, a, ba, cmd, delay):
 116                         r = "\t/* %s */\n" %comment
 117                         r += "\tdfii_pi0_address_write(0x%04X);\n" %a
 118                         r += "\tdfii_pi0_baddress_write(%d);\n" %ba
 119                         if "CKE" in cmd:
 120                                 r += "\tdfii_control_write(%s);\n" %cmd
 121                         else:
 122                                 r += "\tcommand_p0(%s);\n" %cmd
 123                         r += "\tcdelay(%d);\n" %delay
 124                         r += "\n"
 125                         return r
 126
 127
 128                 r += "static void init_sequence(void)\n{\n"
 129
 130                 cl = sdram_phy.phy_settings.cl
 131
 132                 if sdram_phy.phy_settings.type == "SDR":
 133                         bl = 1*sdram_phy.phy_settings.nphases
 134                         mr  = log2_int(bl) + (cl << 4)
 135                         reset_dll = 1 << 8
 136
 137                         init_sequence = [
 138                                 ("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
 139                                 ("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
 140                                 ("Load Mode Register / Reset DLL, CL=%d, BL=%d" %(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
 141                                 ("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
 142                                 ("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
 143                                 ("Load Mode Register / CL=%d, BL=%d" %(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
 144                         ]
 145
 146                 elif sdram_phy.phy_settings.type == "DDR":
 147                         bl = 2*sdram_phy.phy_settings.nphases
 148                         mr  = log2_int(bl) + (cl << 4)
 149                         emr = 0
 150                         reset_dll = 1 << 8
 151
 152                         init_sequence = [
 153                                 ("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
 154                                 ("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
 155                                 ("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
 156                                 ("Load Mode Register / Reset DLL, CL=%d, BL=%d" %(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
 157                                 ("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
 158                                 ("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
 159                                 ("Load Mode Register / CL=%d, BL=%d" %(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
 160                         ]
 161
 162                 elif sdram_phy.phy_settings.type == "LPDDR":
 163                         bl = 2*sdram_phy.phy_settings.nphases
 164                         mr  = log2_int(bl) + (cl << 4)
 165                         emr = 0
 166                         reset_dll = 1 << 8
 167
 168                         init_sequence = [
 169                                 ("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
 170                                 ("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
 171                                 ("Load Extended Mode Register", emr, 2, cmds["MODE_REGISTER"], 0),
 172                                 ("Load Mode Register / Reset DLL, CL=%d, BL=%d" %(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
 173                                 ("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
 174                                 ("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
 175                                 ("Load Mode Register / CL=%d, BL=%d" %(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
 176                         ]
 177
 178                 elif sdram_phy.phy_settings.type == "DDR2":
 179                         bl = 2*sdram_phy.phy_settings.nphases
 180                         mr  = log2_int(bl) + (cl << 4)
 181                         emr = 0
 182                         reset_dll = 1 << 8
 183
 184                         init_sequence = [
 185                                 ("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
 186                                 ("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
 187                                 ("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
 188                                 ("Load Mode Register / Reset DLL, CL=%d, BL=%d" %(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
 189                                 ("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
 190                                 ("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
 191                                 ("Load Mode Register / CL=%d, BL=%d" %(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
 192                         ]
 193
 194                 for comment, a, ba, cmd, delay in init_sequence:
 195                         r += gen_cmd(comment, a, ba, cmd, delay)
 196
 197                 r += "}\n"
 198                 r += "#endif\n"
 199
 200                 return r